Verilog logical (in)equality expression #593
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kroening
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| tc_binary_expr(expr); | ||
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| // This returns 'x' if either of the operands contains x or z. |
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I have to admit that I don't understand how this comment relates to or explains what follows?!
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Maybe by example:
'b0 == 'b0 is 0
'b1x == 'b10 is x
'b1z == 'b1z is x
Hence, if both operands are two-valued, the result is two-valued. If either operand is four-valued, the result is four-valued.
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I understand the example and was assuming as much, but the code that follows just deals with types, it doesn't actually change the expression id or the likes. To me, the comment suggested that the code that follows actually evaluates the expression (or, rather, constructs some code to produce a value for the given operands).
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It does change the ID when it's two-valued -- lines 2431 and 2433.
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Yes, but not in the four-valued case. So I was just a bit confused - but really only by the comment, not the actual implementation.
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Yes, in the four-valued case, the ID stays D_verilog_logical_equality/D_verilog_logical_inequality. I'll add a comment for that.
The Verilog logical equality and inequality now have their own ID as they return a four-valued result when applied to four-valued logic. When applied to two-valued logic, the typechecker maps these to mathematical equality.
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Verilog logical (in)equality expression
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