SystemVerilog: SVA abort properties #618
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| @@ -20,6 +20,10 @@ Author: Daniel Kroening, dkr@amazon.com | |||
| /// sva_s_nexttime φ --> Xφ | |||
| /// sva_if --> ? : | |||
| /// a sva_disable_iff b --> a ∨ b | |||
| /// a sva_accept_on b --> a ∨ b | |||
| /// a sva_reject_on b --> ¬a ∧ b | |||
| /// a sva_sync_accept_on b --> a ∨ b | |||
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Are there really three different ways that all just express disjunction?
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Yes. They differ slightly if you are building a simulator.
This adds SVA abort properties (IEEE 1800-2017 16.12.14).
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SystemVerilog: SVA abort properties
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This adds SVA abort properties (IEEE 1800-2017 16.12.14).