Verilog: KNOWNBUG test for recursive module instantiation #620
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Since Verilog 2005 recursive module instantiation is explicitly allowed. This adds a KNOWNBUG test for this.
tautschnig
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Aug 7, 2024
Romy15200
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Aug 19, 2025
Verilog: KNOWNBUG test for recursive module instantiation
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Since Verilog 2005 recursive module instantiation is explicitly allowed. This adds a KNOWNBUG test for this.