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Netlist conversion: do not convert types #624

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Merged
merged 1 commit into from
Aug 9, 2024
Merged

Netlist conversion: do not convert types #624

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11 changes: 11 additions & 0 deletions regression/verilog/enums/enum1.aig.desc
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Original file line number Diff line number Diff line change
@@ -0,0 +1,11 @@
CORE
enum1.sv
--bound 3 --numbered-trace --aig
^EXIT=10$
^SIGNAL=0$
^\[main\.p1\] always main\.my_light != main.YELLOW2: REFUTED$
^main\.my_light@0 = main\.RED$
^main\.my_light@1 = main\.YELLOW1$
^main\.my_light@2 = main\.GREEN$
^main\.my_light@3 = main\.YELLOW2$
--
2 changes: 2 additions & 0 deletions src/trans-netlist/trans_to_netlist.cpp
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Expand Up @@ -207,6 +207,8 @@ void convert_trans_to_netlistt::map_vars(
else if (symbol.type.id() == ID_module ||
symbol.type.id() == ID_module_instance)
return; // ignore modules
else if(symbol.is_type)
return; // ignore types
else if (symbol.is_input)
vartype = var_mapt::vart::vartypet::INPUT;
else if (symbol.is_state_var)
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