Verilog: add attributes into parse tree #644
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kroening
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| // | attribute_instance_brace udp_instantiation | ||
| // { add_attributes($2, $1); $$=$2; } |
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Why was this always commented out (and still is)?
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The syntax is indistinguishable from the instantiation of normal modules unless a separate token type is used for the identifiers of UDP modules.
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Perhaps you can document this in source via a comment?
| // attribute_instance_brace class_property | ||
| // { add_attributes($2, $1); $$=$2; } | ||
| // | attribute_instance_brace class_method | ||
| // { add_attributes($2, $1); $$=$2; } | ||
| // | attribute_instance_brace class_constraint | ||
| // { add_attributes($2, $1); $$=$2; } |
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Why was/is this commented out?
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Classes are simply not done yet.
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Perhaps this should be documented?
| /* | ||
| module_or_generate_item | ||
| | attribute_instance_brace parameter_declaration { $$=$2; } | ||
| // | attribute_instance_brace local_parameter_declaration { $$=$2; } | ||
| | attribute_instance_brace parameter_declaration | ||
| // { add_attributes($2, $1); $$=$2; } | ||
| // | attribute_instance_brace local_parameter_declaration | ||
| // { add_attributes($2, $1); $$=$2; } | ||
| ; | ||
| */ |
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Why was/is this commented out?
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These are not in the 1800-2017 grammar -- will clean out.
| PRECONDITION(stack_expr(attributes).id() == ID_verilog_attributes); | ||
| if(!stack_expr(attributes).get_sub().empty()) | ||
| addswap(dest, ID_verilog_attributes, attributes); |
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Would it perhaps be better to use ID_C_verilog_attributes? They seem to be ignored during type checking at this point, so I am guessing they don't affect the semantics?
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I don't believe anything with attributes ever gets compared for equality, so it wouldn't make any difference.
The attributes seem to be entirely tool-specific, so there may well be some that have/alter semantics.
I am planning to use them to configure reasoning engines per assertion, but it's not obvious that this is the best mechanism.
Verilog allows attributes (key-value pairs) in various parts of the grammar. These are now added to the generated parse tree.
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Verilog: add attributes into parse tree
Verilog allows attributes (key-value pairs) in various parts of the grammar. These are now added to the generated parse tree.