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KNOWNBUG test for SystemVerilog wildcard equality #657

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Merged
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Aug 31, 2024
Merged

KNOWNBUG test for SystemVerilog wildcard equality #657

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9 changes: 9 additions & 0 deletions regression/verilog/expressions/wildcard_equality1.desc
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Original file line number Diff line number Diff line change
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KNOWNBUG
wildcard_equality1.sv
--bound 0
^EXIT=0$
^SIGNAL=0$
--
^warning: ignoring
--
Missing SystemVerilog wildcard equality implementation.
16 changes: 16 additions & 0 deletions regression/verilog/expressions/wildcard_equality1.sv
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module main;

// wildcard equality operator
// 1800-2017 11.4.6
property01: assert final ((10==?10)===1);
property02: assert final ((10==?20)===0);
property03: assert final ((10!=?20)===1);
property04: assert final ((10==?20)===0);
property05: assert final ((2'b00==?2'b0x)===1);
property06: assert final ((2'b10==?2'b0x)===0);
property07: assert final ((2'b00!=?2'b0x)===0);
property08: assert final ((2'b10!=?2'b0x)===1);
property09: assert final ((1'sb1==?2'b11)===0); // zero extension
property10: assert final ((1'sb1==?2'sb11)===1); // sign extension

endmodule