Skip to content

Verilog: add checks for operators that require integral types #825

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
merged 1 commit into from
Nov 20, 2024

Conversation

kroening
Copy link
Member

This adds checks to the typechecker to enforce that the operands have an integral type.

@kroening kroening force-pushed the must_be_integral branch 5 times, most recently from 4a0e513 to f56d64e Compare November 17, 2024 20:44
This adds checks to the typechecker to enforce that the operands have an
integral type.
@kroening kroening marked this pull request as ready for review November 18, 2024 12:22
@tautschnig tautschnig merged commit 3ea0b0d into main Nov 20, 2024
9 checks passed
@tautschnig tautschnig deleted the must_be_integral branch November 20, 2024 09:11
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
Projects
None yet
Development

Successfully merging this pull request may close these issues.

2 participants