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@kroening kroening commented Dec 2, 2024

This adds SystemVerilog named sequences.

This adds SystemVerilog named sequences.
@kroening kroening force-pushed the verilog-named-sequence branch from 8225c1b to 25636cf Compare December 2, 2024 16:55
@kroening kroening marked this pull request as ready for review December 3, 2024 02:32
@tautschnig tautschnig merged commit 5f864c0 into main Dec 4, 2024
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@tautschnig tautschnig deleted the verilog-named-sequence branch December 4, 2024 10:43
Romy15200 pushed a commit to Romy15200/nws that referenced this pull request Aug 19, 2025
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2 participants