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Verilog: KNOWNBUG for primitive gates with more than two inputs #883

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Merged
merged 1 commit into from
Dec 16, 2024
Merged

Verilog: KNOWNBUG for primitive gates with more than two inputs #883

merged 1 commit into from
Dec 16, 2024

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kroening
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This replicates issue #880.

@kroening kroening marked this pull request as ready for review December 13, 2024 15:57
@tautschnig tautschnig merged commit 216fea0 into main Dec 16, 2024
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@tautschnig tautschnig deleted the or1 branch December 16, 2024 10:32
Romy15200 pushed a commit to Romy15200/nws that referenced this pull request Aug 19, 2025
@tautschnig
Merge pull request diffblue#883 from diffblue/or1
6026326 
Verilog: KNOWNBUG for primitive gates with more than two inputs
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@tautschnig tautschnig tautschnig approved these changes

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