Veriog: synthesis of primitive not gates #884
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For a primitive not gate with input i and output o, this now generates the constraint i = !o as opposed to !i = o While logically equivalent, the new constraint is easier to read, and enables the generation of netlists that are more compact.
tautschnig
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Dec 16, 2024
Romy15200
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Aug 19, 2025
Veriog: synthesis of primitive not gates
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For a primitive not gate with input i and output o, this now generates the constraint
i = !o
as opposed to
!i = o
While logically equivalent, the new constraint is easier to read, and enables the generation of netlists that are more compact.