Verilog: KNOWNBUG test for property ... endproperty #932
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The type checker uses the wrong fragement of the expression syntax for property ... endproperty. Replicates #931.
tautschnig
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Jan 16, 2025
Romy15200
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Verilog: KNOWNBUG test for property ... endproperty
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The type checker uses the wrong fragement of the expression syntax for
property...endproperty.Replicates #931.