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<reg[3] for special meaning.> <I new a project using IAR, and debug it with the IAR simulator. I modified the instruction byte code, and get strange assembles that are not documented. I draw a conclusion in my opinion, for the following instructions: [0 0 0 0 src 1 1 0 0 dst — MOVA Rsrc,Rdst], [0 0 0 0 src 1 1 0 1 dst — CMPA Rsrc,Rdst], [0 0 0 0 src 1 1 1 0 dst — ADDA Rsrc,Rdst], [0 0 0 0 src 1 1 1 1 dst — SUBA Rsrc,Rdst], when src is reg[3], it has special meanings. According to the oper, the Rsrc is MOVA: 0. CMPA: 0. ADDA: 2. SUBA: 2.> #105

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<reg[3] for special meaning.> <I new a project using IAR, and debug it with the IAR simulator. I modified the instruction byte code, and get strange assembles that are not documented. I draw a conclusion in my opinion, for the following instructions: [0 0 0 0 src 1 1 0 0 dst — MOVA Rsrc,Rdst], [0 0 0 0 src 1 1 0 1 dst — CMPA Rsrc,Rdst], [0 0 0 0 src 1 1 1 0 dst — ADDA Rsrc,Rdst], [0 0 0 0 src 1 1 1 1 dst — SUBA Rsrc,Rdst], when src is reg[3], it has special meanings. According to the oper, the Rsrc is MOVA: 0. CMPA: 0. ADDA: 2. SUBA: 2.> #105

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Commits on Jun 5, 2021

  1. reg[3] for special meaning.

    @zhaoleicpp
    zhaoleicpp committed Jun 5, 2021
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