RTL to GDSII using SKY130nm Technology node

Integrated Clock Gating (ICG) Design

TABLE OF CONTENT

I. Introduction to Integrated Clock Gating

II. RTL Design and Synthesis

1. Icarus Verilog (iverilog) & Yosys Installation on Ubuntu
2. RTL Pre-Simulation
3. Synthesis
4. GLS Post-simulation

III. Physical Design from Netlist to GDSII

1. Invoke OpenLane
2. To Build Inverter Standard Cell Design
3. Synthesis
4. Floorplan
5. Placement
6. CTS
7. Routing

Author
Reference
Contributers
Acknowledgment
Contact Information

I. Introduction

The project design is based on Integrated Clock Gating using SKY 130nm technology node.

In current VLSI design, the power dissipation is the most important parameter that signifies the need of low power circuits. In most of the ICs clock consumes 30-40 % of total power. So the integrated clock gating logic is used in many synchronous circuits for reducing dynamic power dissipation, by removing the clock signal when the circuit is not in use.

Block Diagram and Circuit Diagram

Clock gating is a prevailing technique for lowering clock power is done with help of clock enable signal by powering off the module by a clock. Clock gating functionally requires only an AND gate. The former using of AND gate with clock, the high EN edge may arrive at any time and may not coincide with a clock edge. In that case the output of the AND gate will be a logic ‘1’ for less time than the clock’s duty cycle, in turn end up with a glitch in the clock signal. To avoid this, a special kind of clock gating cells are used, that synchronizes the EN with a clock edge. These are called as integrated clock gating cells or ICG. In the design gclk is available only when the latch output is high and gclk is held low when en is low as shown in the circuit diagram. Therefore, target the design very close by meeting the PPA (Power, Performance, Area).

II. RTL Design and Synthesis

1. Icarus Verilog (iverilog) & Yosys Installation on Ubuntu

//Icarus Verilog is an open-source EDA tool for implementing verilog hardware description language//

In the context menu, right click on an empty space, you’ll see the option of ‘Open in Terminal’

• Type the following command to install iverilog & gtkwave

$ sudo apt-get update

$ sudo apt-get install iverilog gtkwave

• Type the following command to install yosys

$ git clone https://github.com/YosysHQ/yosys.git

$ sudo apt install make

$ sudo apt-get install build-essential clang bison flex \
   libreadline-dev gawk tcl-dev libffi-dev git \
   graphviz xdot pkg-config python3 libboost-system-dev \
   libboost-python-dev libboost-filesystem-dev zlib1g-dev
 
$ sudo make install

RTL Pre-Simulation

1. To clone the Repository, type the following commands in your terminal.

$ git clone https://github.com/drvasanthi/iiitb_cg

$ cd /home/vasanthidr11/Desktop/iiitb_cg/

2. Details information of files

3. To Run the .v file, type the following commands

$ iverilog iiitb_icg.v iiitb_icg_tb.v

$ ./a.out
$VCD info: dumpfile iiitb_icg_tb.vcd opened for output.

$ gtkwave iiitb_icg_tb

ICG - Synthesis

1. Invoke the yosys using following commands

// reads the library file from sky130//

yosys> read_liberty -lib ../lib/sky130_fd_sc_hd__tt_025C_1v80.lib

// reads the verilog files//

yosys> read_verilog iiitb_icg.v dff.v

//synthesize the top module of verilog file//  

yosys> synth -top iiitb_icg

//map the FF library file//

yosys> dfflibmap -liberty ../lib/sky130_fd_sc_hd__tt_025C_1v80.lib

//Generates netlist//

yosys> abc -liberty ../lib/sky130_fd_sc_hd__tt_025C_1v80.lib
yosys> stat

//Simplified netlist//

yosys> flatten

//Displays the Netlist circuit//

yosys> show

Synthesized Circuit

//Writing Netlist//

yosys> write_verilog -noattr iiitb_icg_netlist.v
yosys> stat

//Simplified Netlist - As code dwells with additional switch//

yosys> !gvim iiitb_icg_netlist.v

GLS Post-Simulation

Commands to Invoke GLS

$ iverilog -DFUNCTIONAL -DUNIT_DELAY=#1 ../verilog_model/primitives.v ../verilog_model/sky130_fd_sc_hd.v iiitb_icg_synth.v iiitb_icg_tb.v
$ ./a.out
$ gtkwave iiitb.icg_tb.v

Gate Level Simulation

III. Physical Design from Netlist to GDSII

Physical design is process of transforming netlist into layout which is manufacture-able [GDS]. Physical design process is often referred as PnR (Place and Route). Main steps in physical design are placement of all logical cells, clock tree synthesis & routing. During this process of physical design timing, power, design & technology constraints have to be met. Further design might require being optimized w.r.t power, performance and area.

General Physical Design Flow:

1. Invoke Openlane

$ git clone https://github.com/The-OpenROAD-Project/OpenLane.git

Pre-request

• GNU Make

$ sudo apt-get install build-essential
$ sudo apt-get install gcc

• Python 3.6+ with pip and virtualenv

sudo apt install -y build-essential python3 python3-venv python3-pip

• Git 2.22+

sudo apt-get install git

• Docker 19.03.12+

Docker Installlation Instruction

• Setting up OpenLane

cd OpenLane/
    make
    make test

• Magic Installation

$ git clone https://github.com/RTimothyEdwards/magic  
$ sudo apt-get install m4  
$ sudo apt-get install tcl-dev  
$ sudo apt-get install tk-dev  
$ sudo apt-get install blt  
$ sudo apt-get install freeglut3  
$ sudo apt-get install libglut3  
$ sudo apt-get install libglu1-mesa-dev  
$ sudo apt-get install libgl1-mesa-dev  
$ sudo apt-get install csh  
$ ./configure  
$ make  
$ make install  

2. To Build Inverter Standard Cell Design

Step 1: Invoke vsdstdcelldesign

Step 2:

Step 3:

To simulate the inverter, we need a .spice file corresponding to the .mag file. We first extract the .mag file, whcih creates a .ext file in the same directory.

Step 4:

Then we convert the .ext into .spice including all the parasitics.

Step 5:

Edit the .spice file to include model files, define power supply nodes and parasitics

Step 6:

Runing the simulation in ngspice

ngspice sky130_inv.spice  

plot y vs time a

Step 7:

To check whether the first guideline is followed by our inverter, we identify the input and output ports and check if they lie on the intersection of tracks of the corresponding metal by aligning the grids in MAGIC layout to that of the tracks using the grid command in tkcon window. In our case, the porst lie on licon metal, so we align the grid corresponding to those values,

Step 8:

Extract the lef file by typing the command in tkcon window

Save the file

Step 9:

Copy the .lef file and .lib file to the source directory of main design

vasanthi@vasanthi-VirtualBox:~/Desktop/OpenLane/vsdstdcelldesign/libs$ cp sky130_vsdinv.lef /home/vasanthi/Desktop/OpenLane/designs/iiitb_icg/src

vasanthi@vasanthi-VirtualBox:~/Desktop/OpenLane/vsdstdcelldesign/libs$ cp sky130_fd_sc_hd__* /home/vasanthi/Desktop/OpenLane/designs/iiitb_icg/src

3. Synthesis

Synthesis is process of converting RTL (Synthesizable Verilog code) to technology specific gate level netlist (includes nets, sequential and combinational cells and their connectivity).

Step1: To start openlane, we open the shell in openLANE_flow(openlane) directory and run the command,

Step 2:Import openlane packages specifying its version and specify the design that we intend to work on, which is iiitb_icg

This command merges two lefs and places it in a new folder which is named as date and time while running the command, inside directory designs/iiitb_icg/runs/.

Step 3: Include the below command to include the additional lef into the flow:

Step 4: To invoke synthesis

This runs the synthesis where yosys translates RTL into circuit using generic components and abc maps the circuit to Standard Cells.

Physical Cells

• Calcuation of Flop Ratio:

Flop ratio = Number of D Flip flops 
           ______________________
           Total Number of cells

Flop Ratio = 4/8=0.5

Power and Area Report

4. Floorplan

Physical design is process of transforming netlist into layout which is manufacture-able [GDS]. Physical design process is often referred as PnR (Place and Route) / APR (Automatic Place & Route). Main steps in physical design are placement of all logical cells, clock tree synthesis & routing. During this process of physical design timing, power, design & technology constraints have to be met. Further design might require being optimized w.r.t area, power and performance.

Step 1: To invoke floorplan

• Die Area

• Core Area

• Endcap & Tap Cells

Step 2: Opening Floorplan in MAGIC Tool

To view the floorplan created, we need to open it in magic as follows,

The above commmand first reads the tech file which is sky130A.tech, reads lef file which is merged.max.lef and def file which is iiitb_icg.def.

• In the layout, many i/o pins can be seen at the border of the layout, which are equidistant from each other by default.

• • Many tap cells can be seen all over the layout, whcih connect n-well to Vdd and substrate to ground to prevent latch-up. These tap cells are diagonllay equidistant from each other.

• A few standard cells can also been at the lower left corner of the layout.

5. Placement

In this stage, all the standard cells are placed in the design (size, shape & macro-placement is done in floor-plan). Placement will be driven by different criteria like timing driven, congestion driven, power optimization etc. Timing & Routing convergence depends a lot on quality of placement.

Step 1:To invoke placement

Step 2: Opening floorplan in MAGIC

magic -T /home/vasanthi/Desktop/OpenLane/pdks/sky130A/libs.tech/magic/sky130A.tech read ../../tmp/merged.max.lef def read iiitb_icg.def &  

• sky130_vsdinv inside integrated clock gating design

Step 3: Reports

Area Report

Power Report

Setup and Hold Slack

6. Clcok Tree Synthesis (CTS)

Clock Tree Synthesis (CTS) is one of the most important stages in PnR. CTS QoR decides timing convergence & power. In most of the ICs clock consumes 30-40 % of total power. So efficient clock architecture, clock gating & clock tree implementation helps to reduce power.

Step 1: To invoke CTS

Step 2: Reports

• tns & wns report

• Setup & Hold Report

• Power & Area Report

7. Routing

Routing is the stage after Clock Tree Synthesis and optimization where-

• Exact paths for the interconnection of standard cells and macros and I/O pins are determined.
• Electrical connections using metals and vias are created in the layout, defined by the logical connections present in the netlist.

After CTS, we have information of all the placed cells, blockages, clock tree buffers/inverters and I/O pins. The tool relies on this information to electrically complete all connections defined in the netlist such that-

• There are minimal DRC violations while routing.
• The design is 100% routed with minimal LVS violations.
• There are minimal SI related violations.
• There must be no or minimal congestion hot spots.
• The Timing DRCs are met.
• The Timing QoR is good.

Routing is performed in two stages:

• Fast route - Implemented using FastROAD. It generates routing guides.
• Detailed route - Implemented using TritonRoute. It uses the routing guides generated in fast route to find the best route and makes connections.

Step 1: To Invoke Routing

Step 2: Opening Routing in MAGIC Tool

magic -T /home/vasanthi/Desktop/OpenLane/pdks/sky130A/libs.tech/magic/sky130A.tech read ../../tmp/merged.max.lef def read iiitb_icg.def & 

• Post Layout

Step 3: Reports

• Congestion Report

• tns, wns, setup and hold reports

• Power and Area Report

PARAMETER ANALYSIS

1. Post-Layout Synthesis:
** i. Gate count**

Gate Count = 8

ii. Flop Ratio

Flop ratio = Number of D Flip flops / Total Number of cells

Flop Ratio = 4/8 = 0.5

2. Area

Area = 2336.147um2

3. Performance

Performance = (1/clock period - slack) = 1 / (10ns - 4.54ns) = 183.15Mhz

4. Power

Internal Power = 1.24e-04 W
Switching Power = 2.39e-05 W
Leakage Power = 2.06e-10 W
Total Power = 1.48e-04 W

Author

Vasanthi D R

References

[1] VLSI System Design: https://www.vlsisystemdesign.com/

[2] SkyWater SKY130 PDK: https://skywater-pdk.readthedocs.io/en/main/contents/libraries/foundry-provided.html

[3] RTL Design using Verilog with Sky130 Technology: https://www.vsdiat.com/dashboard

[4] Openlane - SKY130: https://github.com/The-OpenROAD-Project/OpenLane

[5] Magic Installation: https://github.com/RTimothyEdwards/magic

Author

Vasanthi D R

Contributors

• Vasanthi D R
• Dantu Nandini Devi
• Kunal Ghosh

Acknowledgement

• Kunal Ghosh, Director, VSD Corp. Pvt. Ltd.
• Nickson Jose, VLSI Engineer, VSD Corp. Pvt. Ltd.
• Madhav Rao, Professor, IIIT-Bangalore.
• Nanditha Rao, Professor, IIIT-Bangalore.
• Efabless Corporation
• Google Skywater Foundry
• Open Road

Contact Information

• Vasanthi D R, PhD Scholar, International Institute of Information Technology, Bangalore vasanthidr11@gmail.com
• Dantu Nandini Devi, MS Student, International Institute of Information Technology, Bangalore nandini.dantu@gmail.com
• Kunal Ghosh, Director, VSD Corp. Pvt. Ltd. kunalghosh@gmail.com
• Madhav Rao, Professor, IIIT-Bangalore. mr@iiitb.ac.in
• Nanditha Rao, Professor, IIIT-Bangalore. nanditha.rao@iiitb.ac.in