bench: Remove add_csr calls (no longer required).

enjoy-digital · Oct 21, 2022 · 15955d8 · 15955d8
1 parent cd42811
commit 15955d8
Show file tree

Hide file tree

Showing 4 changed files with 0 additions and 11 deletions.
diff --git a/bench/arty.py b/bench/arty.py
@@ -47,7 +47,6 @@ def __init__(self, variant="minimal", with_sampler=False, with_analyzer=False, h
             self.submodules.ethphy = LiteEthPHYMII(
                 clock_pads         = self.platform.request("eth_clocks"),
                 pads               = self.platform.request("eth"))
-            self.add_csr("ethphy")
             self.add_etherbone(phy=self.ethphy)
 
         if with_sampler:
@@ -61,7 +60,6 @@ def __init__(self, variant="minimal", with_sampler=False, with_analyzer=False, h
             ]
             self.platform.add_extension(_la_pmod_ios)
             self.submodules.sampler = Sampler(self.platform.request("la_pmod"))
-            self.add_csr("sampler")
 
             # DRAMFIFO -----------------------------------------------------------------------------
             from litedram.frontend.fifo import LiteDRAMFIFO
@@ -113,7 +111,6 @@ def __init__(self, variant="minimal", with_sampler=False, with_analyzer=False, h
                 depth        = 2048,
                 clock_domain = "sys",
                 csr_csv      = "analyzer.csv")
-            self.add_csr("analyzer")
 
 # BenchPHY -----------------------------------------------------------------------------------------
 
@@ -128,7 +125,6 @@ def __init__(self, **kwargs):
         self.platform.add_extension(digilent_arty._sdcard_pmod_io)
         from litesdcard.phy import SDPHY
         self.submodules.sd_phy = SDPHY(self.platform.request("sdcard"), platform.device, self.clk_freq)
-        self.add_csr("sd_phy")
 
         # Send a command with button to verify timings ---------------------------------------------
         self.comb += [

diff --git a/bench/genesys2.py b/bench/genesys2.py
@@ -43,7 +43,6 @@ def __init__(self, with_analyzer=False, host_ip="192.168.1.100", host_udp_port=2
                 clock_pads         = self.platform.request("eth_clocks"),
                 pads               = self.platform.request("eth"),
                 with_hw_init_reset = False)
-            self.add_csr("ethphy")
             self.add_etherbone(phy=self.ethphy)
 
         if with_analyzer:
@@ -66,7 +65,6 @@ def __init__(self, with_analyzer=False, host_ip="192.168.1.100", host_udp_port=2
                 depth        = 2048,
                 clock_domain = "sys",
                 csr_csv      = "analyzer.csv")
-            self.add_csr("analyzer")
 
 # SoC Ctrl -----------------------------------------------------------------------------------------
 

diff --git a/bench/sim.py b/bench/sim.py
@@ -35,7 +35,6 @@ def __init__(self, host_ip="192.168.1.100", host_udp_port=2000):
         data = Signal(8)
         self.sync += data.eq(data + 1)
         self.submodules.sampler = Sampler(data)
-        self.add_csr("sampler")
 
         # DRAMFIFO ---------------------------------------------------------------------------------
         from litedram.frontend.fifo import LiteDRAMFIFO

diff --git a/bench/trellisboard.py b/bench/trellisboard.py
@@ -56,7 +56,6 @@ def __init__(self, variant="minimal", with_sampler=False, with_analyzer=False, h
             self.submodules.ethphy = LiteEthPHYRGMII(
                 clock_pads         = self.platform.request("eth_clocks"),
                 pads               = self.platform.request("eth"))
-            self.add_csr("ethphy")
             self.add_etherbone(phy=self.ethphy)
 
         if with_sampler:
@@ -70,7 +69,6 @@ def __init__(self, variant="minimal", with_sampler=False, with_analyzer=False, h
             ]
             self.platform.add_extension(_la_pmod_ios)
             self.submodules.sampler = Sampler(self.platform.request("la_pmod"))
-            self.add_csr("sampler")
 
             # UDPStreamer --------------------------------------------------------------------------
             from liteeth.common import convert_ip
@@ -111,7 +109,6 @@ def __init__(self, variant="minimal", with_sampler=False, with_analyzer=False, h
                 depth        = 2048,
                 clock_domain = "sys",
                 csr_csv      = "analyzer.csv")
-            self.add_csr("analyzer")
 
 # BenchPHY -----------------------------------------------------------------------------------------
 
@@ -135,7 +132,6 @@ def __init__(self):
         self.platform.add_extension(_sdcard_pmod_ios)
         from litesdcard.phy import SDPHY
         self.submodules.sd_phy = SDPHY(self.platform.request("sdcard_pmoda"), platform.device, self.clk_freq)
-        self.add_csr("sd_phy")
 
         # Send a command with button to verify timings ---------------------------------------------
         self.comb += [