Always arm the "TX FIFO Empty" interrupt after we write into _tx_buffer. #1166
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This avoids a race where the interrupt handler detects an empty _tx_buffer just before we write data into it. Note that commit d6f6294 works around this race when data is continually added to _tx_buffer in the hung state. We revert that change here as the race should no longer occur. Testing performed: - set UART_CONF1.txfifo_empty_thrhd=0x70 (which exacerbates the issue) - generate a ~240 byte burst of data, sent in back-to-back Serial1.write(, 4) calls, optionally followed by a Serial1.flush() Test results: - before this change, observe occasional unsent data and hang in flush() (if used). - after this change, data is sent as expected.
… or _end, even temporarily.
Testing:
- Boot tested, ran basic serial I/O code
Notes:
- Before this change, there are instruction like "s32i.n <reg>, <this>, <_begin>" in the
disassembled output, followed by an overwrite if <reg> turns out to be _bufend.
After this change, there is only one store instruction to <_begin> per function.
…end >= _begin) case.
igrr
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Dec 7, 2015
Always arm the "TX FIFO Empty" interrupt after we write into _tx_buffer.
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This avoids a race where the interrupt handler detects an empty _tx_buffer just before we write data into it.
Note that commit d6f6294 works around this race when data is continually added to _tx_buffer in the hung state (but is not helpful when there is not new data being added). This reverts that change here as the race should no longer occur.
Testing performed:
Test results: