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#4: verilog/VHDL: only generate access signal for specified access mode #27

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merged 2 commits into from
Sep 25, 2022
Merged

#4: verilog/VHDL: only generate access signal for specified access mode #27

merged 2 commits into from
Sep 25, 2022

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v0lker
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@v0lker v0lker commented Sep 9, 2022

see issue #4

@v0lker
esynr3z#4: generate access flags only for the specified access mode
db5cf9f 
e. g. if you specify 'wo' and 'a', you'll only get a *_waccess signal
@v0lker
esynr3z#4: generate access flags only for the specified access modes
d3cb79c 
un-tested implementation of the VHDL part
@v0lker v0lker mentioned this pull request Sep 9, 2022
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@arnfol arnfol added the kind: bug Something isn't working label Sep 18, 2022
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arnfol approved these changes Sep 25, 2022
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Looks good

@arnfol arnfol merged commit b0aca99 into esynr3z:master Sep 25, 2022
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@arnfol arnfol arnfol approved these changes

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