StopWatch

Stopwatch verilog project designed for use on the MAX10 DE-Lite board

Circuit diagrams for some modules:

Name		Name	Last commit message	Last commit date
Latest commit History 8 Commits
BCDEncoder.v		BCDEncoder.v
BCDEncoder_tb.v		BCDEncoder_tb.v
BCDToSevenSeg.v		BCDToSevenSeg.v
BCDToSevenSeg_tb.v		BCDToSevenSeg_tb.v
ClockDivider50MHzTo100Hz.v		ClockDivider50MHzTo100Hz.v
ClockDivider50MHzTo100Hz_tb.v		ClockDivider50MHzTo100Hz_tb.v
Counter18Bit.v		Counter18Bit.v
Counter18Bit_tb.v		Counter18Bit_tb.v
Counter59.v		Counter59.v
Counter59_tb.v		Counter59_tb.v
Counter99.v		Counter99.v
Counter99_tb.v		Counter99_tb.v
JKFlipFlop.v		JKFlipFlop.v
JKFlipFlop_tb.v		JKFlipFlop_tb.v
Mux.v		Mux.v
Mux_tb.v		Mux_tb.v
README.md		README.md
SevenSegEncoder.v		SevenSegEncoder.v
SevenSegEncoder_tb.v		SevenSegEncoder_tb.v
Stopwatch.v		Stopwatch.v
StopwatchLogic.v		StopwatchLogic.v
StopwatchLogic_tb.v		StopwatchLogic_tb.v
Stopwatch_tb.v		Stopwatch_tb.v

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