Skip to content

Audio out

Jump to bottom
foonerd edited this page Nov 2, 2026 · 15 revisions

Audio out

How the player gets audio out of the Waveshare ESP32-C5-Touch-LCD-2.8: what the panel offers any DAC, the options recorded against it, the carrier-board shape that accepts them, the PCM5102A as the worked example of a soldered-down part, and what is still to be proven on the bench. The board itself is on Hardware.

Facts are from the data sheets, manuals, maker pages and schematic listed at the end, read 18 October 2026, and carry their section, table or figure numbers. Bench facts carry their date. Anything not yet measured on a board says so.

Where things stand

Item Standing
DAC No part chosen. Options recorded below against the panel's constraints; the choice is made with a board on the bench, not before.
Wiring to the panel Three I2S lines on fixed header pins, wired and proven on the bench with a Raspberry Pi DAC HAT; see Wiring a Pi-HAT DAC.
Carrier board Not designed. Shape recorded: a Raspberry Pi header and a six-pin module header on the same three lines, plus the PCM5102A footprint as the soldered option. Peter of PIXIS lays it out once the bench has proven the wiring.
Firmware The I2S sink with its software volume, and the register of boards below: a PCM5122, an ES9018K2M or a WM8960 on the header is found and brought up at boot without a word on the card; a board on the three lines alone is named on the card with dac. output chooses between the panel's speaker and the HAT. Every board hears the same stream at the sink's level. The SDK's delivery contract names the sink i2s-dac.
Bench Seven boards proven, each through the sink's volume at 64 fs (32-bit words since 0.2.7; 16-bit words before); they are the register. FLAC and MP3 from the card at real time at 44.1 and 96 kHz; 192 kHz is beyond the chip. What is still to prove is under Still to prove on the bench.

The register

The boards the player knows, by the name the card's dac line takes. A board that answers on the panel's I2C bus is found and brought up at every boot without being named; a board on the three I2S lines alone has nothing to find, so the card names it and the player says what it has in evostatus.txt. Every board hears the same stream at the sink's volume: the slider is one control, and the speaker and the HAT stay level with each other. The stream is 32-bit words in 32-bit slots, the source's bits at the top, and the level is applied in 32-bit, so turning the volume down costs no bits of a 16- or 24-bit source; a DAC of fewer bits takes the top ones.

dac Boards proven Chip How the player knows it What the bring-up does Mute for output = speaker
pcm5102a GY-PCM5102, CJMCU-5102 modules TI PCM5102A named on the card nothing: pins only. SCK to ground; FMT, FLT and DEMP low; XSMT high. GY-PCM5102: solder bridges H1 L, H2 L, H3 H, H4 L, SCK by the pads beside it. none; it plays on
pcm5122 Waveshare PCM5122 Audio Board (A); Raspberry Pi DAC+ (IQaudIO); HiFiBerry DAC+, DAC+ Pro, DAC2 Pro; Allo Boss; InnoMaker DAC Mini TI PCM5122 on the bus at 0x4C or 0x4D PLL on BCK, 16-bit I2S. A board with its own oscillators (the Boss class) has them switched off through the chip's GPIO3 and GPIO6, so the chip follows BCK at every rate. The Pi DAC+ needs 3.3 V on header pin 1 or 17 as well as 5 V. the chip's mute register
es9018k2m Audiophonics I-Sabre K2M class; bare modules ESS ES9018K2M on the bus at 0x48 initialised at its 0 dB; its own clock is on the board the chip's mute bit
es9038q2m InnoMaker HiFi DAC Pro, hardware mode ESS ES9038Q2M named on the card nothing: nothing on the bus to write. 64 fs only; at 32 fs it is overdriven. none; it plays on
wm8960 Waveshare WM8960 Audio HAT Cirrus WM8960 on the bus at 0x1A (it takes writes only; its reset is the probe) PLL from the HAT's 24 MHz, 32-bit I2S, headphones and speakers at 0 dB; written with the clocks stopped at every rate change; silent above 48 kHz the codec's soft mute

output: both (the default) plays the speaker and the HAT; hat switches the speaker's amplifier off and mutes its codec; speaker mutes a HAT found on the bus, and says in evostatus.txt when a named board has no mute to use. A dac name that is not in the register is reported and set aside; a bus board named on the card that does not answer is reported too.

What the board gives a DAC

  • One I2S controller. The ESP-IDF I2S guide for the ESP32-C5: "ESP32-C5 contains one I2S peripheral(s)". It can be master or slave; slots of 8, 16, 24 or 32 bits; an MCLK output is optional. On this board it is wired to the ES8311 codec: BCLK GPIO 24, LRCK GPIO 25, data out GPIO 27, data in GPIO 26 (schematic).
  • No master clock. The ES8311's MCLK pin is not connected (schematic), so the codec takes its main clock from BCLK (ES8311 register 0x01, MCLK_SEL). Nothing on the board offers an MCLK line.
  • Four free GPIOs on two headers. GPIO 2 and GPIO 3 on J8, GPIO 11 and GPIO 12 on J6. J5 is the board's own I2C bus, not free.
  • Power and control on J8. USB 5 V, 3V3, USB D- and D+, and the IO expander's EXIO6 and EXIO7. J8 pin 2 is the USB_5V net, the same net as the USB-C connector's VBUS pins; it feeds the board through D3 and then D2 to the 3.3 V buck converter (schematic), so 5 V on J8 pin 2 powers the panel with USB-C unplugged. There is no diode between J8 pin 2 and the USB-C VBUS pins: with both connected, two 5 V sources are tied together.
  • No analogue output on any header. The ES8311's OUTP and OUTN go only to the NS4150B speaker amplifier, through 100 nF and 150 kohm (schematic).

What any option must fit

Each constraint follows from the list above. An option that fails one is still recorded, with what it would take.

# Constraint Because
1 Run from BCK and LRCK alone, or bring its own master clock The board has no MCLK. Spending GPIO 12 on one is possible but unproven; see Alternatives considered.
2 Control by pins, or by I2C on the panel's own bus The only I2C on offer is J5, with six devices on it at 0x18, 0x24, 0x51, 0x58, 0x6A/0x6B and 0x70. A DAC's address must be none of those.
3 At most one fast GPIO beyond the three I2S lines, plus two slow expander lines GPIO 12 is the only GPIO left. EXIO6 and EXIO7 on J8 are driven over I2C, too slow for a clock but fine for a static reset, mute or clock-select line; the worked example already uses EXIO6 for XSMT.
4 Take 3.3 V logic and its own 3.3 V from 5 V The ESP32-C5's I/O; the panel's 3V3 rail also feeds the radio.
5 Give an output a jack or a speaker can take directly The board has no line, headphone or speaker-level output on any header.

A Raspberry Pi I2S DAC HAT meets 1, 3 and 4 by construction: the Pi's 40-pin header carries no master clock (BCLK on pin 12, LRCLK on pin 35, DIN on pin 40, 5 V on pins 2 and 4, 3.3 V on pins 1 and 17, I2C on pins 3 and 5), so Pi DAC HATs are built without a host MCLK. That market is the first place to look.

The options

Three tiers by what a board needs beyond the three I2S lines and 5 V:

  • Tier 0: nothing. Configured by pins; its own clock if it needs one. Volume is applied to the samples in software.
  • Tier 1: I2C, over a third cable to J5. Hardware volume, read-back, filters. A board that masters the bus from its own clocks is still tier 1; the panel runs as I2S slave. One static line for a reset or a mute is still tier 1: GPIO 12 or an expander line carries it.
  • Tier 2: more lines than that. Recorded; not for this panel without a different carrier.

Status is the maker's own lifecycle word on the date read.

Option Where it comes from Clock Control Volume Output Tier Maker status
TI PCM5102A bare modules (GY-PCM5102 and CJMCU-5102 class, both proven on the bench); Pi HATs that carry it PLL from BCK, SCK grounded pins software 2.1 Vrms line, 1 kohm minimum load 0 Active; TI names the TAD5242 and TAD5212 as its alternates
TI PCM5122 Pi HATs: HiFiBerry DAC+ standard (PLL from BCK); IQaudIO DAC+; HiFiBerry DAC+ Pro and DAC2 Pro, Allo Boss and the boards built to the Boss's overlay (InnoMaker DAC Mini), which carry their own clocks and master the bus on a Pi unless set to slave, with the clocks selected through the PCM5122's own GPIO3 and GPIO6 over I2C. The firmware sees a running oscillator at boot and switches both off through those pins, so every PCM5122 board runs its PLL from BCK PLL from BCK, or the board's own clocks I2C at 0x4C to 0x4F by pins, SPI, or hardware mode hardware 2.1 Vrms line 1 Active
HiFiBerry DAC2 HD Pi HAT: TI PCM1792A DAC at I2C 0x4C and its clock generator at 0x62 (kernel overlay); neither address collides with the panel's devices its own clock circuit; masters the bus I2C for the DAC and the clocks; one reset line on Pi GPIO16, active low hardware line 1, with GPIO 12 on Pi pin 36 as the reset line —
TI TAD5242 no modules known; 24-pin QFN controller or target modes; whether it runs without an MCLK is not yet read from the data sheet pins software 2 Vrms balanced line, 1 Vrms single-ended; headphones at up to 62.5 mW into 16 ohm, pseudo-differential 0 if it needs no MCLK Active; 120 dB dynamic range
TI TAD5212 none known as TAD5242 I2C or SPI hardware as TAD5242 1 Active; the software-controlled twin
ESS ES9023P Pi HATs and modules that carry an oscillator needs an MCLK; the board's oscillator supplies it pins software 2 Vrms line 0 with the oscillator on the board Legacy at ESS (replacement ES9033)
ESS ES9018K2M Pi HATs (Audiophonics I-Sabre K2M, generic) and bare modules; all carry a local clock needs an MCLK; on the board I2C at 0x48 (0x49 to 0x4B on some boards) hardware, 0.5 dB steps current output into the board's op-amp stage, line level 1; runs on power-on defaults without I2C Legacy at ESS (replacement ES9039Q2M / ES9020)
ESS ES9028Q2M Pi HATs of the I-Sabre Q2M class on the board I2C hardware line, via the board's op-amps 1 Legacy at ESS
Cirrus WM8960 Pi HATs: Waveshare's WM8960 Audio HAT, the ReSpeaker 2-Mics class; a codec with a headphone amplifier and 1 W class-D speaker drivers its own 24 MHz oscillator; SYSCLK through the chip's PLL I2C at 0x1A, write-only (the chip answers no read, so a bus scan does not see it; the firmware probes it with a reset) hardware on the headphone and speaker amplifiers; the firmware leaves them at 0 dB and uses the sink's 3.5 mm headphones; two 8 ohm speakers, 1 W each 1 Active; 8–48 kHz only — above that the firmware mutes it and the board plays on, the face's strip saying so
ESS ES9038Q2M Pi HATs and bare modules on the board I2C hardware line, via the board's op-amps 1 Active at ESS (successor ES9039Q2M)
ESS Sabre, part not named HiFiBerry DAC+ Light: "based on an ESS Sabre chip set", GPIO 18–21 only on the board pins software line 0 —
ESS ES9039Q2M, ES9033Q, ES9020 no boards known yet — I2C hardware — — ES9039Q2M and ES9033Q active; the ES9020's status is shown only as an icon on ESS's page; ESS's recommendations for new designs
ADI MAX98357A seven-pin breakouts (LRC, BCLK, DIN, GAIN, SD, GND, VIN) none needed pins (GAIN, SD_MODE) software a speaker: 3.2 W into 4 ohm from 5 V, one channel per chip, SD_MODE picks left, right or the mix; two boards make stereo 0 Production; ADI recommends the MAX98365 for new designs
Cirrus WM8804 Pi HATs of the Digi+ class the board masters I2S from its own crystal; the panel runs as I2S slave I2C at 0x3A or 0x3B, SPI, or hardware mode none (digital) S/PDIF coaxial and TOSLINK, one transmitter 1; the Digi+ Pro adds two clock-select lines on Pi GPIO 5 and 6 Discontinued at Cirrus; data sheet still published
Hymnal a protected board from the Grace project, available to order; Raspberry Pi header the board masters I2S; the panel runs as I2S slave I2C hardware balanced XLR and RCA analogue; AES/EBU, S/PDIF coaxial and TOSLINK digital 1 built, under test
Any other Pi I2S DAC HAT the market, including boards whose chip the maker does not name (HiFiBerry DAC+ Zero: GPIO 18–21 only) no host MCLK, by construction varies varies varies 0 or 1 each resolves to one of the chip rows above once the chip is known

What the tiers cost in firmware: tier 0 is the I2S sink alone; tier 1 adds one driver crate for the chip and one delivery plugin that owns its volume and mute. The sink and the decoder do not change between rows. Where the register facts for a tier-1 chip come from matters: TI, Cirrus and ADI publish their data sheets; ESS does not, and the ES9018K2M is covered instead by the project owner's published Volumio plugin for it, which already drives these registers on Raspberry Pi hardware.

Wiring a Pi-HAT DAC

The bench form, before any carrier board: a Raspberry Pi I2S DAC HAT on jumper wires to the panel's headers. The firmware mirrors the panel's I2S output onto three header pins through the GPIO matrix, so the HAT hears the same frames as the on-board codec.

A Pi-HAT DAC on the panel's headers: BCLK and LRCLK from J8, data from J6, I2C from J5

Signal Pi header pin Panel header pin ESP32-C5 GPIO
BCLK 12 (GPIO 18, PCM CLK) J8 pin 7 GPIO 2
LRCLK 35 (GPIO 19, PCM FS) J8 pin 8 GPIO 3
DATA, into the DAC 40 (GPIO 21, PCM DOUT) J6 pin 2, TXD GPIO 11
GND 6, or any ground pin J8 pin 5, or any ground pin —
SDA, tier 1 only 3 (GPIO 2, SDA1) J5 pin 2 GPIO 0
SCL, tier 1 only 5 (GPIO 3, SCL1) J5 pin 1 GPIO 1

Pin 1 of each panel header is as Waveshare's schematic numbers it; check the silkscreen. J8 is the SH1.0 12-pin header, J6 the UART header and J5 the I2C header, pictured on the companion wiki's Boards page.

  • Power. The HAT takes its 5 V from its own supply, never from J8 pin 2. That pin is the panel's USB-C VBUS with no diode between them, so a HAT's supply on it back-feeds the USB port; on the bench a board fed from that pin put a steady tone on the output, which left with the wire. A board that must run from the panel takes the filter in Powering a DAC board from the panel. Leave every 3V3 pin unconnected; both sides are 3.3 V logic.
  • Clocks. The panel is the I2S master and offers no master clock; a HAT brings its own oscillator, as Pi HATs do by construction.
  • I2C. Only for a tier-1 board. J5 is the panel's own bus, with the six devices and the 2 kΩ pull-ups listed under What any option must fit. The firmware probes 0x48 for an ES9018K2M at every boot and brings one up when it answers; a pins-only board needs nothing said to it.
  • The console. J6 is UART0. The firmware moves the console to the USB Serial/JTAG port so that TXD is free for data; the serial link to a Pi on the companion's Connections page is not available alongside a HAT.
  • Volume. One level for the speaker and the HAT, applied to the samples in the sink from the output subject; the ES8311 and an ES9018K2M sit at full scale.

At boot the firmware logs the pins it drives: i2s0: mirrored for a HAT: BCLK GPIO2 (J8.7), WS GPIO3 (J8.8), DATA GPIO11 (J6 TXD).

Proven on the bench, 18 and 19 October 2026, with an ES9018-based I2S-only HAT on its own clock (tier 0): a 1 kHz tone; FLAC at 44.1 and 96 kHz and MP3 at 44.1 kHz from the card, at real time; the sink's volume at 40 %. Not yet: a tier-1 board on J5, 24-bit audio in 32-bit slots (the sink runs 16-bit slots), the panel as I2S slave.

Carrier board

Two sockets on the same three I2S lines, J5's I2C, 5 V and ground, so that both board families plug in without a new layout:

  • a 2×20 Raspberry Pi header: 5 V on pins 2 and 4; 3.3 V on pins 1 and 17 from the carrier's own regulator, never the panel's 3V3 — not optional: the IQaudIO-design boards (Raspberry Pi DAC+) run their DAC's digital side and I2C from it and are silent without it (bench, 2026-10-30); I2C on 3 and 5; BCLK on 12, LRCLK on 35, DOUT on 40; grounds; GPIO 12 to pin 36 (Pi GPIO16), which is both the panel's one spare fast line and the DAC2 HD's active-low reset; EXIO6 and EXIO7 to pins 29 and 31 (Pi GPIO 5 and 6, the Digi+ Pro's clock-select lines), subject to bench item 3; pins 27 and 28 unconnected, as HiFiBerry asks for the ID EEPROM pins;
  • a six-pin module header: 5 V, GND, BCK, LRCK, DIN and a spare for a mute or enable. 5 V suits the MAX98357A (2.5 to 5.5 V) and modules with their own regulator; a bare 3.3 V-only module takes the carrier's regulator instead;
  • the PCM5102A footprint and its passives, for the soldered option, as detailed below. EXIO6 serves either that footprint's XSMT or the Pi header's pin 29, not both at once;
  • reverse-current protection on the carrier's 5 V feed to J8 pin 2, since the panel ties it to its USB-C VBUS without a diode; otherwise the panel's USB-C must stay unused while the carrier powers it.

Series-resistor footprints on the three lines at the sockets, fitted with 0 ohm until the bench says otherwise. HiFiBerry's position on cabled HATs: not a supported configuration, use a full 40-pin ribbon, and "don't even try long 30-50cm cables". Keeping the three lines the same length is this page's advice, not theirs.

Powering a DAC board from the panel

J8 pin 2 is the panel's USB-C VBUS, straight through: the ESP32-C5's Wi-Fi bursts, its buck converter and the backlight PWM all ride on it. A DAC board fed from that pin hummed on the bench; on its own supply it was clean. This filter on the wire lets a board run from the panel again, and is the shape of the carrier board's 5 V entry.

Inline 5 V filter from J8 to a DAC board

An RLC pi filter, overdamped, with reverse protection on the panel side. Panel to board, in order:

Ref Part Role
D1 Schottky, SS34 or 1N5819 (3 A; about 0.3 V at 200 mA) A board on its own supply never pushes into the panel's USB port. Leave it out only if the board is always fed through this filter and the 0.3 V is needed.
C1, C2 100 uF 10 V electrolytic; 100 nF X7R Panel-side reservoir, so the wire does not carry the panel's noise out.
FB Ferrite bead, 600 ohm at 100 MHz, 2 A or more RF: Wi-Fi and converter edges.
L1 33 uH shielded power inductor, saturation 1 A or more, DCR 0.1 ohm or less The LC corner.
R1 1 ohm, 0.5 W Damping (Q about 0.18 against C3, no peaking) and an RC corner. A 0 ohm link for a board with a 5 V analogue stage.
C3 1000 uF 10 V low-ESR electrolytic or polymer The LC and RC bulk.
C4, C5 10 uF X7R; 100 nF X7R Soldered at the board's header; what the electrolytic's inductance lets through.

Corners: LC at about 876 Hz, RC at about 159 Hz; roughly 20 to 35 dB down across 1 to 3 kHz, 55 dB at 10 kHz, 60 dB or more from 100 kHz up (limited by the capacitors' ESR and ESL). Drop at 200 mA about 0.5 V (D1 0.3, R1 0.2, the inductor's DCR 0.02), so about 4.5 V at the board from a 5.0 V VBUS: fine for I2S-only boards with their own 3.3 V regulators, and the reason for the 0 ohm option where a board runs an analogue stage from 5 V.

Build it as a string on a twisted pair under 30 cm, both wires from J8 (pins 1 and 2, not ground from J6), heatshrink on each joint, C4 and C5 at the board's header. The board's audio ground stays the board's; nothing else grounds to the panel.

To check it: the board on a bench supply (the reference), then on bare J8 pin 2, then through the filter. An oscilloscope AC-coupled at the board's 5 V pin, 20 MHz bandwidth limit, with Wi-Fi joined and the backlight on; then the ear. A tone that survives at the same pitch is coming through the return path, not the rail. If more is ever needed, a second RC stage (another 1 ohm and 1000 uF) buys 20 dB a decade for another 0.2 V, or feed the filter from a separate 5 V supply with D1 left out.

3.3 V for the header's pins 1 and 17

Some boards take more than 5 V from the header. The IQaudIO design (the Raspberry Pi DAC+) runs its PCM5122's digital side, and so its I2C, from the Pi's 3.3 V rail on pins 1 and 17, and uses the 5 V for the analogue stage: on 5 V alone it is silent and absent from the bus, which is how the bench found this. Waveshare's and HiFiBerry's boards regulate everything from 5 V and do not care. The rail is small — a HAT's logic draws tens of milliamps — but it must be there, and it is not the panel's own 3V3 (J5 pin 3, J8 pin 6), whose regulator carries the ESP32-C5, the display and the radio. A low-noise LDO after the 5 V filter is the stage:

3.3 V for a HAT: a low-noise LDO after the 5 V filter to header pins 1 and 17

Filter to header, in order:

Ref Part Role
U1 LP5907MFX-3.3 (TI, SOT-23-5): 250 mA, 120 mV dropout, 6.5 uVrms noise, PSRR 60 dB at 100 kHz. The TPS7A2033 is TI's newer drop-in at 300 mA. The regulator. Its enable pin is tied to its input, so the 3.3 V follows the 5 V with no sequencing.
C6 1 uF X7R at IN The input capacitor the data sheet asks for.
C7 1 uF X7R at OUT The output capacitor the data sheet asks for; ceramic.
C8 10 uF X7R at the header, pin 1 to ground The reservoir the board sees.

Numbers: the filter delivers about 4.5 V at 200 mA, so the LDO has 1.2 V of headroom over its 0.12 V dropout; it dissipates 1.2 V × I — 60 mW at 50 mA, 180 mW at 150 mA, about +34 °C in a SOT-23-5 at 150 mA, and a HAT's logic draws far less. Keep the LDO within a few centimetres of the header and link pins 1 and 17 there. A drawer AMS1117-3.3 module works too: it drops 1.1 V, so feed it from before R1 of the 5 V filter, and it is ordinary on noise.

On the bench the Raspberry Pi DAC+ ran with 3.3 V jumpered from the panel's J8 pin 6 to pin 1 — enough to prove the board, not the arrangement to keep: the carrier board gets this stage.

The worked example: TI PCM5102A

The soldered-down option, worked through to component values because its data sheet allows it. Everything in this section is specific to this part.

Property Value Source
Status Active TI product page
Data 16, 20, 24 or 32-bit, two's complement, MSB first; I2S or left-justified Data sheet 9.3.2.2, Table 2
Sample rates 8 to 384 kHz; in PLL mode see the firmware section Data sheet, Features; Table 11
SNR, THD+N 112 dB, -93 dB TI product page
Output 2.1 Vrms, ground-centred, no DC-blocking capacitors; loads 1 to 10 kohm Data sheet, Features; 8.3
Clocking An internal PLL makes the system clock from BCK when SCK is held at ground: a 3-wire connection 9.3.5.3, 9.4.1
Control Pins only: FMT, FLT, DEMP, XSMT Section 7
Supplies AVDD and CPVDD 3.3 V; DVDD 1.8 or 3.3 V 8.3, Table 12
Inputs Failsafe LVCMOS Schmitt-trigger, 1.8 or 3.3 V logic Section 7, footnote
Package TSSOP-20 (PW) Table 1

The data sheet (SLAS859C) covers the PCM5100A, PCM5101A, PCM5102A and their -Q1 parts; the values here are the PCM5102A's.

How it meets the constraints:

  1. Its PLL generates the system clock from BCK; with SCK grounded the connection is BCK, LRCK and DIN only.
  2. It is configured by four pins and has no I2C.
  3. It needs one line beyond I2S, for XSMT, and the IO expander provides it.
  4. Its inputs take 3.3 V logic; it runs from its own regulator.
  5. Its 2.1 Vrms ground-centred outputs go to a jack through a small filter, with no coupling capacitors.

What it does not do:

  • No hardware volume. Volume is applied to the samples in software.
  • Not a headphone driver. Its minimum load is 1 kohm. A headphone socket needs an amplifier after it.
  • No read-back. The firmware cannot ask it whether it is locked, muted or powered down.

Wiring

flowchart LR
    subgraph panel["ESP32-C5-Touch-LCD-2.8"]
        direction TB
        i2s["I2S TX<br/>BCK, WS, DOUT"]
        exp["CH32V003 expander"]
    end
    subgraph carrier["Carrier board"]
        direction LR
        buf["Buffer"]
        dac["PCM5102A"]
        ldo["3.3 V regulator<br/>from 5 V"]
        jack["Line out jack"]
    end
    i2s -- "BCK: GPIO 2, J8 pin 7" --> dac
    i2s -- "LRCK: GPIO 3, J8 pin 8" --> dac
    i2s -- "DIN: GPIO 11, J6 pin 2" --> dac
    exp -- "EXIO6, J8 pin 9" --> buf
    buf -- "XSMT" --> dac
    ldo -- "AVDD, CPVDD, DVDD" --> dac
    dac -- "OUTL, OUTR through 470 ohm and 2.2 nF" --> jack
Loading
PCM5102A pin Name Connects to Note
13 BCK GPIO 2, J8 pin 7 I2S bit clock
15 LRCK GPIO 3, J8 pin 8 I2S word clock
14 DIN GPIO 11, J6 pin 2 (UART TXD) I2S data
12 SCK Ground Starts the PLL: 3-wire mode (9.3.5.3)
16 FMT Ground I2S format
11 FLT Ground Normal-latency filter
10 DEMP Ground De-emphasis off
17 XSMT EXIO6, J8 pin 9, through a single-gate buffer at the DAC end Low mutes, high plays. The data sheet asks for rise and fall times under 20 ns (9.3.3), which a resistor pull-up through a cable would not meet. Pull-down and pull-up footprints at the buffer's input, one fitted after bench item 3.
1, 8, 20 CPVDD, AVDD, DVDD 3.3 V from the carrier board's regulator See Carrier board
3, 9, 19 CPGND, AGND, DGND Ground, shared with J8 pins 1 and 5 and J6 pin 4
6, 7 OUTL, OUTR The jack, through the output filter
2, 4, 5, 18 CAPP, CAPM, VNEG, LDOO Capacitors only See Carrier board

Left free: GPIO 12 (J6 pin 1) and EXIO7 (J8 pin 10). Not used by the DAC: the panel's 3V3 on J8 pin 6 and J6 pin 3; the DAC has its own regulator.

Why these pins

  • Strapping. GPIO 2 and GPIO 3 are strapping pins, MTMS and MTDI, both floating by default (ESP32-C5 data sheet, Table 3-1). MTDI selects the SDIO sampling edge (3.2, Table 3-4); MTMS has no function described. Normal SPI boot depends only on GPIO 28 being high (3.1, Table 3-3). The data sheet adds that a pin "connected to an external high-impedance circuit" keeps its internal default (Section 3). BCK and LRCK take them into high-impedance DAC inputs, and the carrier board puts no pull resistor on either. On the bench the panel boots and plays with both wired to a HAT.
  • Boot messages. GPIO 11 is UART0 TXD, where the ROM prints its boot messages by default (3.3, Table 3-5). DIN takes it rather than a clock: during boot BCK is idle, so the DAC has no valid clocks and does not power up (PCM5102A 11.5.2), and the text cannot reach the output. To confirm by listening through a reset; bench item 2.
  • The spare line. GPIO 12 is UART0 RXD, with its weak pull-up on at reset (ESP32-C5 data sheet, Table 2-1). Held high through reset, it suits an active-low reset such as the DAC2 HD's: released until the firmware drives it.
  • The console. J6 is UART0, the serial console by default. A board with this DAC moves the console to USB Serial/JTAG (GPIO 13 and 14, J8 pins 3 and 4). The serial link to a Raspberry Pi on the companion wiki's Connections page is not available alongside it.
  • Two cables. The three I2S lines cross both J8 and J6. At 48 kHz and 64 fs, BCK is 3.072 MHz, a period of about 325 ns; at 192 kHz it is 12.288 MHz, about 81 ns. Keep both cables short and the same length. The series-resistor footprints on the carrier board are there if the bench shows ringing.

The three lines and the two cables are the same for every option on this page; only the PCM5102A's own pins (SCK, FMT, FLT, DEMP, XSMT) are specific to it.

Parts and values

Values from the data sheet's typical application (Figure 33), output filter note (8.5, note 3) and layout guidance (Section 12):

Part Value Where
Supply decoupling 0.1 uF and 10 uF on each of AVDD, CPVDD and DVDD As close to the pins as possible (12.1)
LDOO 0.1 uF Table 12
Charge pump Two 2.2 uF: the flying capacitor across CAPP and CAPM, and VNEG to ground Figure 33; confirm the placement against the figure when laying out
Output filter, each channel 470 ohm in series, 2.2 nF to ground 8.5 note 3, Figure 33
BCK, LRCK, DIN Series-resistor footprints at the DAC end, fitted with 0 ohm until the bench says otherwise
XSMT A single-gate 3.3 V buffer at the DAC end, for edges under 20 ns (9.3.3); footprints for a pull-down to ground and a pull-up to 3.3 V at its input, fit one; a 0 ohm footprint across the buffer in case the bench shows it is not needed Bench item 3

Power:

  • Feed AVDD, CPVDD and DVDD from a low-noise 3.3 V regulator on the carrier board, supplied from the 5 V the carrier board passes to the panel on J8 pin 2. The panel's own 3V3 also supplies its Wi-Fi radio.
  • DVDD at 3.3 V matches the ESP32-C5's I/O; the internal LDO then makes the 1.8 V core rail (Table 12).
  • One ground. The data sheet allows AGND and DGND to be joined (12.1) and requires all grounds within 0.2 V of each other (8.3, note 1). Keep the clock lines away from the analogue outputs (12.1).

Output:

  • OUTL and OUTR through the filter straight to a 3.5 mm or RCA jack, the carrier board's choice. No coupling capacitors.
  • Line level only. Headphones need an amplifier stage, not chosen.

Power-down:

  • The planned shutdown takes XSMT low at least 150 sample periods plus 0.2 ms before power is removed, or stops the clocks 3 ms before (11.2.1). With XSMT on EXIO6 the firmware can do the first.
  • A power switch that cuts 5 V without the firmware's knowledge needs the unplanned-shutdown arrangement instead: XSMT sensing the supply ahead of the regulator, which the data sheet allows in parallel with a controller's GPIO (11.2.2, Figure 38).

Firmware

The sink, the ES8311 driver, the ES9018K2M driver, the PCM512x driver and the WM8960 driver exist in the firmware for this board; the per-family delivery plugins do not yet. At boot the player lists every address on the header's bus that answers (in the log and in evostatus.txt), then brings up what it recognises: an ES9018K2M at 0x48 by its status register; a PCM5121/PCM5122 at 0x4C or 0x4D by two of its reset values (the chip has no identity register), configured as the Linux pcm512x driver configures a Pi HAT with no master clock — PLL on BCK, the clock dividers left to the chip, 16-bit I2S, 0 dB; a WM8960 at 0x1A by whether it takes a reset (it answers writes only), its PLL set from the HAT's 24 MHz for the stream's rate, 16-bit I2S, headphones and speakers at 0 dB. A board with no I2C part is seen as nothing on the bus and simply plays. What is common to every option, then what the PCM5102A adds.

A codec on the header is written to only while the I2S clocks are stopped: the sink stops them for a rate change, the codecs are told the new rate in that gap, and the clocks start again. The WM8960's control interface has no glitch filter to speak of and took the bit clock on the header's wires as noise. The header's bus runs at 100 kHz for the same part (its SCL low time is 1.3 µs minimum).

For every option:

  • The sink. The panel's I2S peripheral in standard (Philips) mode, stereo, on the codec's pins and mirrored through the GPIO matrix onto BCK GPIO 2, WS GPIO 3, DOUT GPIO 11, MCLK unused (I2S_GPIO_UNUSED). The panel is I2S master for a tier-0 or tier-1 DAC; it is I2S slave (I2S_ROLE_SLAVE, BCLK and WS as inputs on the same pins) for a board that masters the bus from its own clock, as digital-out HATs generally do and as Hymnal does.
  • Slot width. In ESP-IDF the slot width is the number of BCLK ticks per slot: 16 bits gives 32 fs, 32 bits gives 64 fs. The sink runs 32-bit words in 32-bit slots, Philips-shifted, so the bit clock is 64 fs — the frame every Pi HAT DAC takes. The decoder hands the sink its samples in the stream's own width (16-bit for 16-bit material, 32-bit for wider); the sink widens each sample to 32 bits and applies the volume there, so turning the level down costs the source no bits. It ran 16-bit words in 16-bit slots until a Sabre board in hardware mode read the 32 fs frame as wrong words and played them loud, deaf to the volume; the PCM5122 had accepted both. A 24-bit slot would give 48 fs, which few DACs' PLLs accept.
  • The speaker. The NS4150B is held off by a 10 kohm pull-down on its enable until EXIO3 drives it high (schematic, R21). The firmware enables it, so the speaker plays the same frames as a HAT; a delivery plugin that owns an external DAC will leave it off. The ES8311's DAC can also be powered down over I2C.
  • Volume. One level on the output subject, applied to the samples in the sink before they reach I2S; the ES8311 and an ES9018K2M sit at full scale. Tier 1 later: the DAC's own registers, through that chip's delivery plugin.
  • Sink name. i2s-dac, as the delivery contract in sdk/src/contract/audio.rs names it.

For the PCM5102A:

  • BCK ratio. BCK must be 32 or 64 times the sample rate; the PLL takes nothing else (9.3.5.3, Table 11).
  • Rates in PLL mode (Table 11). 16 kHz at 64 fs only; 32, 44.1, 48, 96, 192 and 384 kHz at 32 or 64 fs; 8 kHz not at all.
  • Mute. XSMT low before the clocks stop, before a sample-rate change and before power-down; high once the clocks are running. The ramp takes about 104 samples (9.3.3).
  • What the DAC does by itself.
    • It mutes after 1024 LRCK periods of zero data, about 21 ms at 48 kHz (9.3.2.3).
    • It drops to standby on a clock error or halt, and powers down when BCK and LRCK stay low for more than a second (11.5.2).
    • It powers up again when valid clocks return.

Keeping the microphone

If the ES8311's microphone has to work while the DAC plays (voice control has been asked about), the codec still needs BCLK and LRCK on GPIO 24 and 25 while the DAC takes them on GPIO 2 and 3. The clocks on both pin sets are what the firmware already does; the microphone alongside is not tried:

  • One signal on several pins. The ESP32-C5 manual says "the output signal from a single peripheral can be sent to multiple pins simultaneously" (TRM 8.5.4, note). It lists I2SO_BCK_out and I2SO_WS_out as matrix signals 13 and 14 (Table 8.12-1).
  • Shared clocks. In full duplex, the TX and RX channels share BCLK and WS (ESP-IDF I2S guide).
  • The codec's clock. The ES8311 can take its main clock from BCLK and multiply it by 1, 2, 4 or 8 (registers 0x01 MCLK_SEL, 0x02 MULT_PRE), so 64 fs times 4, or 32 fs times 8, makes 256 fs. With a multiplier of 4 or 8, the pre-divided clock must exceed 1 MHz at DVDD 3.3 V (recommended operating conditions, note 1). The codec's DVDD on this board is 3.3 V (schematic, R18). At 48 kHz, 64 fs is 3.072 MHz and 32 fs is 1.536 MHz.

The ESP-IDF I2S driver configures one pin per signal. The second set would be routed through the GPIO matrix directly, outside the driver.

Alternatives considered

What the register leaves out, and why.

Option Why not
ES8311 mono line out Not reachable from a carrier board. OUTP and OUTN go only to the amplifier, and no header carries them (schematic). It would mean a wire soldered to the panel.
The speaker header The NS4150B's bridged output, for a speaker only. Neither a line nor a headphone output. A MAX98357A board is the recorded way to a better speaker.
A DAC that needs the panel's master clock Constraint 1. GPIO 12 could carry MCLK: the manual lists I2S_MCLK_out as matrix signal 12 (Table 8.12-1). Unproven. Boards that bring their own oscillator (the ESS boards for the Pi) do not need this.
Boards that want more than one static line (HiFiBerry Digi+ Pro: clock select on Pi GPIO 5 and 6) Tier 2 on GPIO 12 alone. On the carrier's Pi header EXIO6 and EXIO7 reach pins 29 and 31, which would cover it; that depends on the expander's output type, bench item 3. The DAC+ Pro needs no host line (its clocks are selected through the PCM5122 over I2C) and the DAC2 HD needs one (reset on GPIO16, which GPIO 12 reaches on pin 36): both are tier 1.
Headphones The PCM5102A's minimum load is 1 kohm, so not from it. The TAD5242 and TAD5212 drive headphones at up to 62.5 mW into 16 ohm and may be the answer, pending the MCLK question; their output is pseudo-differential, so the jack's sleeve goes to the chip's common output, not to ground. No other row drives headphones.

Still to prove on the bench

Breakout boards and HATs first, with jumper leads to J8, J6 and, for tier 1, J5. Boards differ in how they set configuration pins and whether they bring their I2C out: read the listing and the silkscreen before connecting. For a PCM5102A module, check that SCK is grounded and FMT, FLT, DEMP and XSMT are as in the wiring table.

Proven on the bench so far, through the sink's volume:

Board Chip On the bus Brought up Heard
Waveshare PCM5122 Audio Board (A) TI PCM5122 0x4C by the firmware: PLL on BCK, 32-bit I2S 44.1 kHz at 32 fs and at 64 fs. The Pi sees it as an IQaudIO DAC+; it has no clock of its own and plays nothing until configured.
InnoMaker HiFi DAC Pro ESS ES9038Q2M (the maker's listing), in hardware mode 0x30 (the board's own part; not a DAC address; nothing written to it) needs nothing 96 kHz at 64 fs. At 32 fs it was overdriven and deaf to the volume.
Raspberry Pi DAC+ (the IQaudIO Pi-DAC+ design) TI PCM5122 0x4C by the firmware, as the Waveshare board 96 kHz at 64 fs. Needs 3.3 V on pin 1 or 17 as well as 5 V: the IQaudIO design runs the chip's digital side, and so its I2C, from the Pi's 3.3 V rail; with 5 V alone it is silent and absent from the bus. The Waveshare and HiFiBerry designs regulate everything from 5 V.
# What Why How
1 Sound at 44.1 and 48 kHz, 16-bit and 24-bit in 32-bit slots, from a tier-0 board The basic claim, for the whole register Done at 44.1 and 96 kHz in 16-bit slots (tone, FLAC, MP3; 18 and 19 October 2026). Open: 48 kHz, and 24-bit in 32-bit slots.
2 The ROM's boot text on DIN stays silent The pin choice above Listen through a reset and a power-up
3 EXIO6's output: push-pull or open-drain, its high level, and the edge times at XSMT Decides the PCM5102A's XSMT arrangement and whether EXIO6 and EXIO7 can serve a HAT's reset or clock-select pins on the Pi header. The expander runs Waveshare's firmware, and the driver has no read-back of its configuration. XSMT wants edges under 20 ns (9.3.3). Measure with both XSMT footprints empty. Push-pull: fit the pull-down, so the DAC stays muted until the firmware unmutes it. Open-drain: fit the pull-up. Scope the edges at XSMT, and keep the buffer unless they are under 20 ns without it.
4 Signal integrity over the two cables BCK up to 12.288 MHz at 192 kHz, across two cables Scope BCK at the DAC at the highest rate used
5 A tier-1 board on J5 alongside the panel's six devices Pull-ups in parallel, addresses, bus speed The firmware already probes 0x48 at every boot; no tier-1 board has been attached yet. Then volume and mute through its registers
6 The panel as I2S slave to a board that masters the bus Digital-out HATs; Hymnal Lock, then a test tone, with the board's clock
7 Clocks on both pin sets, the ES8311's microphone working alongside Keeping the microphone Route BCK and WS to both sets; record from the microphone while playing
8 Decode headroom on one core Which codecs and rates decode in time; the ceiling for every row; see Hardware Measure with the decode plugin
9 J8 pin 2 as a 5 V input with USB-C unplugged Boards with their own supply feed the panel, not the reverse Settled on paper: J8 pin 2 is the USB_5V net, through D3 and D2 to the 3.3 V buck (schematic), with no diode towards the USB-C VBUS pins. Remaining: measure it, and the carrier's reverse-current protection.
10 A headphone stage Only if a headphone socket is wanted Choose a part. Not started.

Sources

Support evo-esp32.

evo-esp32 is designed, built and maintained by one developer in his own time. If it has earned a place on your bench:

Provided as-is under the Business Source License 1.1; sponsorship is a thank-you, not a purchase: it buys no priority, no features and no support agreement. evo™ and evoframework™ are trademarks of Just a Nerd.

evo-esp32

Clone this wiki locally