This project has been developed as part of the "Reti Logiche" course at Politecnico di Milano, academic year 2017/2018. It is also considered as part of the bachelor degree thesis. All the project has been developed in italian, the code has been written in VHDL. This repo contains the code (project 1) as well as the code documentation and the specifics.
The project consists in the implementation of an HW component which, given an image in grey scale pixels, computes the area of the minimal rectangle which completely includes an object in the image itself. "includes" means that aLl the pixels which are part of the object should be part of the rectangle as well( or at least be part of the perimeter).
The component is described and synthetized in VHDL, and communicates with a memory where the image is stored and where the component should write the value of the area.
For more information, refer to the specs.
The synthesis tool is XILINK. VIVADO WEBPACK.