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Specified the status of the VRAM DMA register once a transfer is done. #624

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Specified the status of the VRAM DMA register once a transfer is done. #624

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4b39a2d
Update CGB_Registers.md
Phidias618 Sep 14, 2025
333c116
Update CGB_Registers.md
Phidias618 Sep 14, 2025
f03e6f7
Update CGB_Registers.md
Phidias618 Sep 14, 2025
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Moved the description of the state of the VRAM DMA source and destina…
Phidias618 Sep 26, 2025
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Update src/CGB_Registers.md
Phidias618 Sep 27, 2025
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2 changes: 2 additions & 0 deletions src/CGB_Registers.md
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Expand Up @@ -39,12 +39,14 @@ tested on Echo RAM, OAM, FEXX, IO and HRAM\]. Trying to specify a source
address in VRAM will cause garbage to be copied.

The four lower bits of this address will be ignored and treated as 0.
The address specified by those registers is cached internally and incremented by $10 for each block of $10 bytes successfully transferred. The cached address persists until the registers are written again.

#### FF53–FF54 — HDMA3, HDMA4 (CGB Mode only): VRAM DMA destination (high, low) \[write-only\]

These two registers specify the address within 8000-9FF0 to which the
data will be copied. Only bits 12-4 are respected; others are ignored.
The four lower bits of this address will be ignored and treated as 0.
The address specified by those registers is cached internally and incremented by $10 for each block of $10 bytes successfully transferred. The cached address persists until the registers are written again.

#### FF55 — HDMA5 (CGB Mode only): VRAM DMA length/mode/start

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