Using Ruby-CHI as a soft NoC for cosimulation with Xiangshan tile

[shinezyy]

To scale to many-core architecture, the L2 cache ports of Xiangshan core has been modified to support CHI (Xiangshan-L2-with-CHI-ports). However, there is not yet an open-source implemention of CHI NoC in RTL (neither Verilog nor Chisel).

We plan to tailor ICN/HNF from Ruby-CHI of GEM5 for co-simulation with Xiangshan processor. To achieve this, we are building an L2 wrapper to connect ICN with Xiangshan Tile (consisting of core and L2). Then L2 wrapper, ICN, HNF, and SNF will be instantiate with cxx-config.

There will be serveral patches:
First, we will enable cxx-config for RISC-V.
Then, we will seperate HasDownStream from AbstractCacheController, because only down stream node info are necessary for co-simulation, but many pure virtual functions are not. In addition, some functions like functionalRead() is infeasible for an RTL cache.
Finally, if possible, we want to provide a "Hello-world" example of co-simulating with an RTL RNF.

[shinezyy]

Suggested labels for this issue:

arch-riscv
mem-ruby
enhancement