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"I didn't know it was IMPOSSIBLE!... I just needed it." - 400k+ Context on Qwen 3.6 MoE 35B on a Single 16GB GPU (RTX 5060 Ti) at 25 t/s #28584
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🚀 UPDATE: Breaking the limits on an RTX 5090 32GB!Just wanted to update this thread! Yesterday, we conducted the exact same stress-test architecture, but this time on a flagship RTX 5090 32GB GPU. And the results are absolutely mind-blowing:
After the massive ~10-minute prefill phase, we ran a thorough sanity check testing the model on complex isolated code generation and abstract logic. The Qwen 3.6 MoE model remained 100% coherent, fully responsive, and perfectly functional, generating pristine code structures at a blistering 35 tok/s! And yes — the entire 1.5M context pipeline runs COMPLETELY inside a single GPU! No system RAM offloading, no dual-card setups. Just raw, optimized single-card dominance. 🦖🔥🏆 |
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For anyone wondering why this fits at all, it's mostly the architecture: Qwen3.6-35B-A3B keeps a KV cache in only 10 of its 40 layers (the rest are linear attention with a fixed-size state), with 2 KV heads × 256. That's 20 KiB per token at f16 and ~10.6 KiB at q8_0. At 354K tokens it's ~6.75 GiB at f16 and ~3.6 GiB at q8_0, so next to an ~11 GiB file it only fits on 16 GB with a quantized cache. If you'd rather keep a 4-bit quant than a 2.68 bpw one: UD-Q4_K_M (22.1 GB file) at 128K with f16 KV needs I built a free planner that picks the |

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Hi everyone!
People often tell me that something is "impossible"... but when it actually works, they suddenly have nothing to say.
They claim that a 10M context with 90%+ coherence is undoable? Well, Grok publicly rated my solution on X (Twitter) as a 9.8 out of 10... for achieving a 60M context with 90%+ coherence.
Today, I want to share a successful stress-test optimization that allowed me to push the Qwen 3.6 MoE (35B-A3B) model far beyond its native limits on a single consumer-grade RTX 5060 Ti 16GB GPU, while keeping all 99 layers completely in VRAM.
My Setup & Metrics
Key Takeaways
Deep Dive & The Solution (How to bypass HTTP 400 & Capping)
Standard parameters like
qwen2.context_lengthor barecontext_lengthoverrides were ignored by the recentllama-serverbuilds with CUDA 13.3, forcing a 256k slot cap. The hard limit of the model was successfully forced-overridden via the correct metadata key:--override-kv qwen35moe.context_length=int:400000.Here is the exact launch command that made this rock-solid stable:
What do you think? Who can replicate or beat this result?
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