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Revise pattern to fix Coq/Verilog misclassification #4751

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Revise pattern to fix Coq/Verilog misclassification #4751

wants to merge 2 commits into from

Commits on Dec 18, 2019

  1. Revise some pattern for avoding Coq/Verilog misdetection

    @yumaueda
    yumaueda committed Dec 18, 2019
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  2. Add a sample Verilog file used to be misclassified as Coq.

    @yumaueda
    yumaueda committed Dec 18, 2019
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