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runtime: add async preemption support to the riscv port #36711
It has been a month since this issue was reported. Is there any work in progress?
I am new here but I have experience tracing/tweaking RISC-V context handling in Linux kernel. Now PPC64 and MIPS* async-preemption support are fine references, so I'll start from their ports. Any other hints are welcomed.
The infinite loop can be successfully preempted and thus release the main goroutine, but when it reached the end of this test case, the
The other issue is choosing which register to be clobbered.
I expect to send this patch in a few weeks, hopefully not months.
I'm not sure LR is a good choice. For frameless leaf functions LR is live throughout the entire function. We don't want the whole function be non-preemptible.
On the other hand, the TMP register is only live across sequences of a small number of instructions. It is used for synthesize large offsets, etc. In particular, it won't make an entire loop non-preemptible. It looks to me the usage of REGTMP on RISCV is pretty much the same as on MIPS or ARM64. (Note that we only care code generated by the Go compiler, not assembly code.)