New snippets for Verilog and some reorganization

UltiSnips/systemverilog.snippets

@@ -0,0 +1 @@
+extends verilog

UltiSnips/verilog.snippets

@@ -0,0 +1,16 @@
+snippet in "Input"
+input${1: [${2:n}:${3:0}]} ${0:name}
+endsnippet
+
+snippet out "Output"
+output${1: reg}${2: [${3:n}:${4:0}]} ${0:name}
+endsnippet
+
+snippet reg "Register variable"
+reg${1: [${2:n}:${3:0}]} ${4:name};
+endsnippet
+
+snippet wire "Wire variable"
+wire${1: [${2:n}:${3:0}]} ${4:name};
+endsnippet
+

UltiSnips/verilog_systemverilog.snippets

@@ -0,0 +1 @@
+extends systemverilog