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SuperTrans, Superscalar Transactional memory simulator, is a multicore, cycle-accurate and multiple issue simulator built on top of the SuperESCalar (SESC) framework that is capable of simulating three of the most common dimensions of hardware transactional memory (Eager/Eager, Eager/Lazy, Lazy/Lazy).
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hughes-c/SuperTrans
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HOW TO setup sesc/SuperTrans ----------------------- This README provides a quickstart guide for setting up and running your first benchmark on SuperTrans. SuperTrans is built on top of SESC, which can be found at: http://sourceforge.net/projects/sesc/ building sesc/SuperTrans and running your first benchmark ---------------------------------------------------- 1) create a build directory > mkdir bin We recommend that you have one build directory per simulator set of options. You may create as many directories as you want and compile the simulator with different combinations of options (see step 3). 2) go to the build directory > cd bin 3) configure SESC/SuperTrans from build > ../src/configure --enable-transactional # Note for debugging builds # ../src/configure --enable-transactional --enable-debug 4) build sesc/SuperTrans: > make 5) copy example configuration files > cp ../confs/* . 6) run test benchmark > ./sesc.trans ../benchmarks/testBench directory structure ------------------- src - supertrans source code benchmarks - precompiled transactional benchmarks docs - autogenerated doxygen documentation confs - example configuration files FAQ --- This is a pre-release, however with the final release more thorough documentation will be included.
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SuperTrans, Superscalar Transactional memory simulator, is a multicore, cycle-accurate and multiple issue simulator built on top of the SuperESCalar (SESC) framework that is capable of simulating three of the most common dimensions of hardware transactional memory (Eager/Eager, Eager/Lazy, Lazy/Lazy).
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