GitHub - iamirfan786/verilog-gate-array: Simple gate array design in Verilog with testbench and Makefile for simulation.

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Simple gate array design in Verilog with testbench and Makefile for simulation.

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Name		Name	Last commit message	Last commit date
Latest commit History 1 Commit
Makefile		Makefile
gate_array.v		gate_array.v
tb_gate_array.v		tb_gate_array.v

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Simple gate array design in Verilog with testbench and Makefile for simulation.

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