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iamrk-vlsi/README.md
  • 👋 Hi, I’m Rohit Kankal
  • 👀 I’m interested in RTL,FPGA Design, Computer Architecture,5G PHY,RISC-V,Neuromorphic Computing,AI/ML,Flexible Electronics,etc
  • 🌱 I’m currently learning Digital and Analog ASIC Design.
  • 💞️ I’m looking to collaborate on RTL Design,Verification, and FPGA projects.
  • 📫 How to reach me : rohitkankal.vlsi@gmail.com

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  1. RISC-V-MYTH-Workshop RISC-V-MYTH-Workshop Public

    5 days (30 hours) is all what took me to learn the basics and design a pipelined RV32I core. Check this article to know more !

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