[SPIR-V] Initial support of FPGA loop attributes/pragmas

[MrSidims]

Following attributes/pragmas are supported:

ivdep
ivdep safelen (N)
ii(N)
max_concurrency_loop(N)
LLVM IR ->SPIRV translation (appropriately the set order):

!"llvm.loop.ivdep.enable ->
4 LoopMerge {{[0-9]+}} {{[0-9]+}} 4
!"llvm.loop.ivdep.safelen", i32 N ->
5 LoopMerge {{[0-9]+}} {{[0-9]+}} 8 N
!"llvm.loop.ii.count", i32 N ->
6 LoopMerge {{[0-9]+}} {{[0-9]+}} 0x80000000 5889 N
!"llvm.loop.max_concurrency.count", i32 N ->
6 LoopMerge {{[0-9]+}} {{[0-9]+}} 0x80000000 5890 N
Also a case of multiple bit masks set for LoopControl is
now supported.

SPEC: KhronosGroup/SPIRV-Registry#28

Signed-off-by: Dmitry Sidorov dmitry.sidorov@intel.com

[bader]

I think it would be useful to add a tag to this commit.
Something like "[SPIR-V] Add initial support for FPGA loop attributes/pragmas".

[bader]

I think it would be useful to add a tag to this commit.
Something like "[SPIR-V] Add initial support for FPGA loop attributes/pragmas".

This request is about changing the commit message, not the PR title.
NOTE: we use "rebase and merge" strategy, so PR title is not recorded in the git - only your commits.