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A small selection of fixes to increase the pass rate of the enqueue CTS
unit tests:

  • Blocking memory reads/writes now properly wait on the queue.
  • urKernelSetArgMemObj added to the function table.
  • Debug print removed.
  • Layout of kernel arguments now matches the HIP target if Offload is on
    an AMD device.
  • urEnqueueEventsWaitWithBarrierExt has been implemented (it just
    calls to the non-ext version).
  • UR_DEVICE_INFO_TIMESTAMP_RECORDING_SUPPORT_EXP set to false.

PlatformName.data(), nullptr);
if (strcmp(PlatformName.data(), "CUDA") == 0) {
triple = "nvptx64-nvidia-cuda";
} else if (strcmp(PlatformName.data(), "AMDGPU") == 0) {
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don't love the use of strcmp but I do recognize that this is moved, not new

A small selection of fixes to increase the pass rate of the enqueue CTS
unit tests:
* Blocking memory reads/writes now properly wait on the queue.
* `urKernelSetArgMemObj` added to the function table.
* Debug print removed.
* Layout of kernel arguments now matches the HIP target if Offload is on
  an AMD device.
* `urEnqueueEventsWaitWithBarrierExt` has been implemented (it just
  calls to the non-ext version).
* `UR_DEVICE_INFO_TIMESTAMP_RECORDING_SUPPORT_EXP` set to false.
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RossBrunton commented Sep 2, 2025

@intel/llvm-gatekeepers I think this is ready to merge.

The failure in L0 is unrelated, as this code doesn't touch cmake and this failure affects other commits ( intel/llvm/actions/runs/17310765995/job/49144828656?pr=19921 ).

EDIT: #19944

@uditagarwal97 uditagarwal97 merged commit 36419ab into intel:sycl Sep 2, 2025
46 of 49 checks passed
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3 participants