[SPIR-V][DOC]Add extension doc for SPV_INTEL_memory_access_aliasing #3426

MrSidims · 2021-03-26T14:10:36Z

Signed-off-by: Dmitry Sidorov dmitry.sidorov@intel.com

sycl/doc/extensions/SPIRV/SPV_INTEL_memory_access_aliasing.asciidoc

AlexeySachkov · 2021-03-26T14:50:40Z

sycl/doc/extensions/SPIRV/SPV_INTEL_memory_access_aliasing.asciidoc

+scope. When evaluating an aliasing query if two memory access instructions that
+have _AliasScopeMaskINTEL_ and _NoAliasMaskINTEL_ memory operands or decorated
+with _AliasScopeINTEL_ and _NoAliasINTEL_ decorations and if for some domain,
+the set of scopes with that domain in one instruction’s aliasing scope list is a
+subset of (or equal to) the set of scopes for that domain in another
+instruction’s noalias list, then the two memory accesses are assumed not to
+alias.


This seems like a pretty generic description of the overall mechanism/idea, should it be moved somewhere else, like overview?

Also,

if two memory access instructions that have AliasScopeMaskINTEL and NoAliasMaskINTEL memory operands

Does this spelling assume that those memory instructions have both of those operands at the same time? Or one has the first one and another the second one?

I have moved this text to overview and explicitly specify "Or one has the first one and another the second one?".

Does this spelling assume that those memory instructions have both of those operands at the same time? Or one has the first one and another the second one?

Yes, a single instruction can have both memory operands simultaneously in case if they have different scope, like

%var = OpLoad %type %ptr1 (noalias 1, alias 2) OpStore %ptr2 %var (noalias 1) OpStore %ptr3 %var (alias 2)

AlexeySachkov · 2021-03-26T14:50:59Z

sycl/doc/extensions/SPIRV/SPV_INTEL_memory_access_aliasing.asciidoc

+
+
+Optional <id> _Name_ parameter is used to specify an unique domain in global
+scope. If this rule is violated in runtime - behaviour is undefined.


Which rule?

Moved it to overview.

sycl/doc/extensions/SPIRV/SPV_INTEL_memory_access_aliasing.asciidoc

MrSidims · 2021-03-29T12:21:44Z

Thanks for the suggestions! I'll apply them a bit later. For now I answer the most important one, that affects the actual implementation.

This extension adds analogs of alias.scope and noalias metadata in SPIR-V. These metadata is being used to annotate non-aliasing memory accesses and being generated, for example, during inlining of functions with restrict pointer parameters. This patch also casually adds OpDecorateId in the translator flow. Spec: intel/llvm#3426 Signed-off-by: Dmitry Sidorov <dmitry.sidorov@intel.com>

* Implement SPV_INTEL_memory_access_aliasing extension This extension adds analogs of alias.scope and noalias metadata in SPIR-V. These metadata is being used to annotate non-aliasing memory accesses and being generated, for example, during inlining of functions with restrict pointer parameters. Spec: intel/llvm#3426 This patch also casually adds OpDecorateId in the translator flow. Signed-off-by: Dmitry Sidorov <dmitry.sidorov@intel.com>

* Implement SPV_INTEL_memory_access_aliasing extension This extension adds analogs of alias.scope and noalias metadata in SPIR-V. These metadata is being used to annotate non-aliasing memory accesses and being generated, for example, during inlining of functions with restrict pointer parameters. Spec: intel#3426 This patch also casually adds OpDecorateId in the translator flow. Signed-off-by: Dmitry Sidorov <dmitry.sidorov@intel.com> Original commit: KhronosGroup/SPIRV-LLVM-Translator@974749c

Signed-off-by: Dmitry Sidorov <dmitry.sidorov@intel.com>

MrSidims · 2021-04-13T09:44:26Z

Resolved comments with a simple fix, answered others.

It should be a valid case if alias.scope and noalias mask/decoration be applied to the same instruction. Signed-off-by: Dmitry Sidorov <dmitry.sidorov@intel.com>

sycl/doc/extensions/SPIRV/SPV_INTEL_memory_access_aliasing.asciidoc

* Implement SPV_INTEL_memory_access_aliasing extension This extension adds analogs of alias.scope and noalias metadata in SPIR-V. These metadata is being used to annotate non-aliasing memory accesses and being generated, for example, during inlining of functions with restrict pointer parameters. Spec: intel/llvm#3426 This patch also casually adds OpDecorateId in the translator flow. Signed-off-by: Dmitry Sidorov <dmitry.sidorov@intel.com>

AlexeySotkin · 2022-01-24T09:59:00Z

@MrSidims any plans finishing this PR?

MrSidims · 2022-01-24T10:05:52Z

@MrSidims any plans finishing this PR?

I was thinking, that everything is in place. Let me double check/resolve comments.

Modify headers to include declarations of tokens described by this spec: intel/llvm#3426

MrSidims · 2022-10-14T12:16:32Z

sycl/doc/extensions/SPIRV/SPV_INTEL_memory_access_aliasing.asciidoc

+This extension adds *AliasDomainDeclINTEL*, *AliasScopeINTEL* and
+*AliasScopeListDeclINTEL* instructions that serve a purpose to
+specify aliasing scopes within which annotated memory accesses don't alias.
+Results of these instructios are used by *AliasScopeINTEL* and *NoAliasINTEL*


Suggested change

Results of these instructios are used by *AliasScopeINTEL* and *NoAliasINTEL*

Results of these instructions are used by *AliasScopeINTEL* and *NoAliasINTEL*

MrSidims · 2022-10-14T12:16:43Z

sycl/doc/extensions/SPIRV/SPV_INTEL_memory_access_aliasing.asciidoc

+[width="40%",cols="25,25"]
+|========================================
+| Last Modified Date | 2021-02-15
+| Revision           | A


Suggested change

| Revision | A

| Revision | 2

MrSidims requested a review from a team as a code owner March 26, 2021 14:10

MrSidims requested review from AlexeySachkov and AlexeySotkin March 26, 2021 14:11

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Implement SPV_INTEL_memory_access_aliasing extension KhronosGroup/SPIRV-LLVM-Translator#966

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MrSidims added 2 commits April 13, 2021 12:38

Add extension doc for SPV_INTEL_memory_access_aliasing

11114c6

Signed-off-by: Dmitry Sidorov <dmitry.sidorov@intel.com>

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Signed-off-by: Dmitry Sidorov <dmitry.sidorov@intel.com>

MrSidims force-pushed the private/MrSidims/MemAccessDoc branch from c7cf02d to 2431e36 Compare April 13, 2021 09:41

bader added spec extension All issues/PRs related to extensions specifications SPIR-V Issues related to SPIRV-LLVM-Translator labels Apr 29, 2021

Remove alias.scope/noalias exclusive restriction

96cc162

It should be a valid case if alias.scope and noalias mask/decoration be applied to the same instruction. Signed-off-by: Dmitry Sidorov <dmitry.sidorov@intel.com>

MrSidims commented Jul 15, 2021

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MrSidims changed the title ~~Add extension doc for SPV_INTEL_memory_access_aliasing~~ [SPIR-V][DOC]Add extension doc for SPV_INTEL_memory_access_aliasing Oct 13, 2021

Finally remove mutually exclusive restriction

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MrSidims requested a review from a team as a code owner January 24, 2022 10:31

DmitryBushev added a commit to DmitryBushev/SPIRV-Headers that referenced this pull request Feb 3, 2022

Implement SPV_INTEL_memory_access_aliasing extension

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Modify headers to include declarations of tokens described by this spec: intel/llvm#3426

DmitryBushev mentioned this pull request Feb 3, 2022

Implement SPV_INTEL_memory_access_aliasing extension KhronosGroup/SPIRV-Headers#265

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Implement SPV_INTEL_memory_access_aliasing extension (#265)

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Modify headers to include declarations of tokens described by this spec: intel/llvm#3426

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		Optional <id> _Name_ parameter is used to specify an unique domain in global
		scope. If this rule is violated in runtime - behaviour is undefined.

	Results of these instructios are used by AliasScopeINTEL and NoAliasINTEL
	Results of these instructions are used by AliasScopeINTEL and NoAliasINTEL

[SPIR-V][DOC]Add extension doc for SPV_INTEL_memory_access_aliasing #3426

[SPIR-V][DOC]Add extension doc for SPV_INTEL_memory_access_aliasing #3426

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