_Wires underneath Logics

[mkorbel1]

Description & Motivation

Refactored Logic to hold its value on a _Wire which can be shared across many Logics that are connected to each other. This has two big benefits:

• Improved simulation performance by reducing the number of glitches that need to propagate during combinational logic
• Decreases the stack requirements to help mitigate this issue: Long combinational chains of logic can reach stack size limit during simulation #194

Related Issue(s)

Helps mitigate #194

Testing

• Added new tests where corner cases could have been introduced around combinational logic propagation and edge listening.
• Ran the (limited) existing benchmark suite and observed slight performance improvement. The existing pipeline benchmark is not sufficient probably to show the true benefit for larger designs, though.

Backwards-compatibility

Is this a breaking change that will not be backwards-compatible? If yes, how so?

Sort of, posedge and negedge will now throw an Exception if the width is not 1.

Documentation

Does the change require any updates to documentation? If so, where? Are they included?

No

[eric-norige]

This refactor seems good to me. Is there any measurement on sim performance speed improvement? Do we need a benchmark suite of designs and stimulus to simulate to identify progress/regressions on simulation performance?

[mkorbel1]

Is there any measurement on sim performance speed improvement?

The one benchmark that's currently in the repo showed some modest relative improvement in simulation performance, but it's not a very meaningful measurement or dramatic difference.

Do we need a benchmark suite of designs and stimulus to simulate to identify progress/regressions on simulation performance?

Yes! I don't have them available and haven't had time to develop them, though. If you (or anyone else) is interested in developing some or contributing existing things that could be reused as benchmarks it would be greatly valuable!

And thank you for taking a look!