Implement a stage register module

[jardhu]

This PR creates a StageReg module as specified in #91, and also changes both pipelined CPU models to utilize it.

One thing I wish to improve about the interface, though I do not know how, is to allow users to access the module's inner register in the same way as regular registers, like so:

val if_id = Module(new StageReg(new IFIDBundle))
if_id.pc := ... 
if_id.pcPlusFour := ...

The current interface exposes the register through io.in and io.data, which obscures what the module is supposed to replace and wastes keystrokes.

[jardhu]

Hey @powerjg, when you have time could you look at this PR? I'll need it merged for the non combinational CPU.

[powerjg]

Sorry this took me so long. I scheduled time for it a few different times but things kept coming up. I have a few minor requests below. Generally, I really like the interface, and I'm impressed with your scala magic!

[powerjg]

Great idea! please open an issue :)

[powerjg]

Looks like all of the comments were addressed, though I didn't look closely. Thanks!

[jardhu]

There's one more thing I need to do, which is to remove the compileOptions parameter from the StageReg.