Cores based on the 6144 kHz PLL cause timing errors in MiSTer sys_top

[jotego]

Most timing errors seem benign. A lot of them seem to come from signals going through two different clock domains. Some even have synchronizers but are not detected as such by the tool, or maybe you have to be specific about synchronizers in the SDC file.

All cores are tagged as JTFRAME_NOSTA on MiSTer in 5803857. This probably needs a lot of changes in MiSTer's sys_top.

[jotego]

Tagged JTFRAME_NOSTA for jtframe_pll6293 cores (s16/outrun/shanon) in 54fb40c

[jotego]

And also jtframe_pll6671 (rastan)

[jotego]

SDC constraints were not applied correctly because the pll game was different in each case. Fixed in 8765cd7