Skip to content
View khandelwalkshitij's full-sized avatar
🛰️
Busy.
🛰️
Busy.

Organizations

@pixxelhq

Block or report khandelwalkshitij

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Please don't include any personal information such as legal names or email addresses. Maximum 100 characters, markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse

Pinned Loading

  1. computer-architecture-lab computer-architecture-lab Public

    Lab Work for CS F342 (Computer Architecture) course, BITS Pilani

    Verilog 4

  2. CommSysLab CommSysLab Public

    Lab work for EEE F311 (Communication Systems) Course at BITS Pilani. The content is made available strictly for learning purposes.

    MATLAB 4 2

  3. lowrisc-chip lowrisc-chip Public

    Forked from lowRISC/lowrisc-chip

    The root repo for lowRISC project and FPGA demos.

    SystemVerilog 1

  4. SimpleVOut SimpleVOut Public

    Forked from cliffordwolf/SimpleVOut

    A Simple FPGA Core for Creating VGA/DVI/HDMI/OpenLDI Signals

    Verilog 1

  5. hFE-tester hFE-tester Public

    A Microprocessor Transistor h-FE tester to display the h-FE value of NPN transistors.

    Assembly 2

  6. anantanurag/CSF342-16bit-Proc anantanurag/CSF342-16bit-Proc Public

    16 Bit RISC Processor

    Verilog 1