RISC-V (RV32IMAC) Implementation in NSL

• This repository contains implementation of RV32IMAC(currently supporting RV32IMA,Zicsr,Zifencei,SV32, simple PMAs and some delegation to S-Mode with User-Mode and Supervisor-Mode, Machine-Mode except for PMP, HPM).
• This implementation is fully synthisable and also able to convert to software simulator(by verilator).
• Written in NSL

NSL

• NSLCORE is compiler tool for NSL.
• NSLCORE can convert NSL code into either Verilog HDL, VHDL, SystemC.
• You can download Trial version of Windows binary of NSLCORE from NSLCORE Overtone(en) or NSLCORE Overtone(ja). (registration is required, limitation of non-comercial use and code size for trial version (2000 lines?) )
• Currently over 2000 lines(must remove empty lines after preprocessing)
• You can also download LiveCygwin which provides minimum? environment of Cygwin without installing.
• LiveCygwin includes verilator, gtkwave, iverilog, vim, NSLCORE and some implementation examples in NSL.
• If you need Linux version of NSL compiler, please consult Overtone.

Documentations of NSL

• NSL Reference en and NSL Reference ja
• NSL Tutorial (registation is required)

Prerequisites

• Installation of Docker
• Installation of X11 (if you want to debug with GTKWave)
• Quartus or other synthesis tools (if you want to implement this system on FPGA)

Prepare Development environment

• Required tools are built in Dockerfile.

Build image

$ cd image
$ ./build.sh # This will create docker image (Take some time to finish)

Run container

$ ./run.sh # This will run bash in docker container

riscv-tests

• Implementation can be tested with riscv-tests.
• To test, run following commands.
• Writting to tohost(0x80001000) will cause simulator to finish its simulation with written value as exit code.
  in 'logs' directory, we can find instruction execution trace. If tests failed, then 'failed' directory will be created and failed test and its vcd will copied into it for debugging.
• Test will result in passed, failed or timeout. Timeout means simulator has potential bugs which result in infinite loop.
• Reset vector is 0x00000000. Bootrom is placed on address location of 0x00000000 to 0x00001000.
• Bootrom contains code to jump to 0x80000000 which test codes are placed.
• Passed Tests STATUS.md

$ cd simulation
$ make run_riscv_tests

dhrystone

Sample apps

xv6

cd software/xv6
make run

OpenSBI

cd software/opensbi
make run

linux

git clone https://github.com/koyamanX/linux.git
cd linux
# TODO: write instruction to build & run linux on simulator

Executing arbitary executable file

• You can simply give executable file to its first arguments.
• If none is given, then a.out in current directory is assumed.
• If writting or reading locations not allocated explicitly in executable file will cause simulator to finish its execution with error message.

rv32x_simulation options

• Simulator executable takes at least one positional argument, RISCV32-little ELF executable.

$ cd simulation
$ ./rv32x_simulation [Name_Of_ELF_File] [Options]

[Options]

Options are prefixed with --.

• print-all (Print execution trace)
• no-sim-exit (Instruct simulator not to exit on writting data to 0x80001000)

TODO

• See Issues and Projetcs pages.

Contribution

Lisence