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22 Open 29 Closed
22 Open 29 Closed
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Issues list

PLIC does not accept interrupts under certain circumstances
#61 opened Sep 27, 2021 by koyamanX
1
Inference of memory block in cache module
#60 opened Sep 27, 2021 by koyamanX
1
Add context 1 to plic to support supervisor external interrupts in core0.
#59 opened Dec 27, 2020 by koyamanX
Some byte in D$ entry are incorrect in some condition where SV32 enabled.
#58 opened Dec 20, 2020 by koyamanX
1
Change interface of UART(uart_sender, uart_receiver) to UART 16550 compliant.
#56 opened Nov 20, 2020 by koyamanX
1
Correct spelling mistakes in projects
#54 opened Nov 16, 2020 by koyamanX
1 task
Extend physical address space to 34 bits
#51 opened Nov 9, 2020 by koyamanX
Replace simple protocol for system bus with AHB-Lite.
#50 opened Oct 10, 2020 by koyamanX
Arbitrate memory access from Instruction Bus and Data Bus
#49 opened Oct 10, 2020 by koyamanX
1
Supporting of N extensions
#47 opened Oct 10, 2020 by koyamanX
Delegation of exceptions to supervisor mode from machine mode.
#46 opened Oct 10, 2020 by koyamanX
Inference of memory block in BTB
#45 opened Oct 10, 2020 by koyamanX
Imprecise instret register
#44 opened Sep 25, 2020 by koyamanX
imprecise implementation of fence instruction.
#43 opened Sep 22, 2020 by koyamanX
1
Add interrupt enable to UART module
#39 opened Aug 31, 2020 by koyamanX
1
Consideration of removal of check_daddr_range in rv32x_mcore module
#38 opened Aug 31, 2020 by koyamanX
Implement Hardware Performance Monitor
#37 opened Aug 25, 2020 by koyamanX
Address range check for MMIO devices and CLINT
#34 opened Aug 24, 2020 by koyamanX
Integrate RSP server to simulation module
#32 opened Aug 23, 2020 by koyamanX
Add mechanism for physical memory protection, attribute
#31 opened Aug 23, 2020 by koyamanX
Refactoring debug signals
#10 opened Aug 10, 2020 by koyamanX
1
1
Possible deadlock in execute stage on issuing system instructions
#1 opened Aug 2, 2020 by koyamanX
ProTip! Exclude everything labeled bug with -label:bug.