• Custom schematic and layout libaries for hardware

    5 7 Updated Nov 3, 2016
  • streaming analysis scripts for WillowGUI

    Python Updated Aug 31, 2016
  • snapshot analysis scripts for willowGUI

    OpenEdge ABL Updated Aug 24, 2016
  • GUI software for the Willow electrophysiology system

    Python 2 Updated Aug 22, 2016
  • [INACTIVE] C and C++ library for STM32 ARM Cortex-M3 development boards.

    C 231 170 Updated Jul 28, 2016
  • _Leaf_Labs electroph_ys_iology _d_aemon

    C 2 2 Updated Jul 12, 2016
  • Documentation for LeafLabs' libmaple and Maple IDE

    Python 8 7 Updated May 4, 2016
  • Symbol and Footprint libraries for KiCad

    1 Updated Apr 8, 2016
  • HDL for the Willow electrophysiology system.

    Verilog 2 1 Updated Mar 1, 2016
  • Verilog Data Model for simulation of Intan RHD2000 Series Electrophysiology Interface Chips

    Verilog Updated Jan 17, 2016
  • little python helpers for parsing through Xilinx build outputs

    Python 3 2 Updated Aug 12, 2014
  • A simple template for simple FPGA projects (mostly Verilog HDL and Xilinx Toolchain)

    Verilog 5 3 Updated May 2, 2014
  • Development environment for the Maple ARM Cortex-M3 development board; forked from Arduino

    Java 43 24 Updated Apr 30, 2014
  • leaflabs.com website

    CSS 1 2 Updated Apr 30, 2014
  • Bootloader firmware for the Maple ARM Cortex-M3 development board from LeafLabs

    C 68 77 Updated Apr 23, 2014
  • buildroot patches for zynq platforms

    C 2 7 Updated Feb 11, 2014
  • utility for debugging Linux UIO ("Userspace I/O") devices

    C 3 3 Updated Dec 21, 2013
  • Current LeafLabs projects -- demos, etc.

    C 13 8 Updated Feb 14, 2013
  • Wiring Framework

    Java 2 134 Updated Aug 21, 2012
  • Maple Mini schematics and layout

    42 33 Updated Jul 24, 2012
  • Maple Native schematics

    Python 11 12 Updated Jul 21, 2012
  • LeafLabs Maple Hardware Design Files

    49 28 Updated Jul 21, 2012
  • Spartan 3E/Cortex M3 interface board

    Prolog 13 5 Updated Jun 30, 2012
  • Maple II Hardware design

    3 5 Updated May 1, 2012
  • For HDL files, FPGA cores etc.

    Verilog 2 2 Updated Apr 10, 2012
  • Restructured text and Sphinx bridge to Doxygen

    Python 1 61 Updated Aug 23, 2011
  • KiCad Maple port for RET6 chip

    4 5 Updated Jun 16, 2011