(1.34.3 backport) [WireDFT] Add support for wiring optional clock div bypass signal. (#5219) #5225
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…5219) If a signal is annotated as the clock divider bypass signal, wire it to clock gates that have the expected port. Like test_en wiring the port number is hardcoded, but unlike test_en this ignores the "bypass" port if that port doesn't match the expected bypass port name/dir/type. Warning is emitted if looks compatible but name doesn't match and bypass signal annotation is found.
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dtzSiFive
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May 17, 2023
| @@ -34,14 +35,14 @@ firrtl.circuit "Simple" { | |||
| // CHECK: firrtl.module @A(in %test_en: !firrtl.uint<1>) | |||
| firrtl.module @A() { | |||
| %in, %test_en, %en, %out = firrtl.instance eicg @EICG_wrapper(in in: !firrtl.clock, in test_en: !firrtl.uint<1>, in en: !firrtl.uint<1>, out out: !firrtl.clock) | |||
| // CHECK: firrtl.connect %eicg_test_en, %test_en : !firrtl.uint<1>, !firrtl.uint<1> | |||
| // CHECK: firrtl.strictconnect %eicg_test_en, %test_en : !firrtl.uint<1> | |||
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The backport picks up a move to emitConnect instead of creating ConnectOps directly, but this should be very safe in terms of WireDFT changes.
seldridge
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May 18, 2023
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Backport this change to 1.34.x .