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[PipelineToHW] Rework hardware lowering #5234

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merged 2 commits into from
Jun 1, 2023

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mortbopet
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@mortbopet mortbopet commented May 19, 2023

This PR reworks hardware lowering to be based on the new pipeline.stage operation introduced in #5246.

Two lowering options are available, inline and outline lowering.

Given an input:

hw.module @testMultiple(%arg0 : i32, %arg1 : i32, %go : i1, %clk : i1, %rst : i1) -> (out: i32) {
  %0 = pipeline.pipeline(%arg0, %arg1, %go) clock %clk reset %rst : (i32, i32, i1) -> i32 {
  ^bb0(%arg0_0: i32, %arg1_1: i32, %arg2: i1):
    %output, %valid = pipeline.stage ins %arg0_0, %arg1_1 enable %arg2 : (i32, i32) -> (i32) {
    ^bb0(%arg3: i32, %arg4: i32, %arg5: i1):
      %2 = comb.add %arg3, %arg4 : i32
      pipeline.stage.return regs %2 valid %arg5 : (i32)
    }
    pipeline.return %output valid %valid : i32
  }
  %1 = pipeline.pipeline(%0, %0, %go) clock %clk reset %rst : (i32, i32, i1) -> i32 {
  ^bb0(%arg0_0: i32, %arg1_1: i32, %arg2: i1):
    %output, %valid = pipeline.stage ins %arg0_0, %arg1_1 enable %arg2 : (i32, i32) -> (i32) {
    ^bb0(%arg3: i32, %arg4: i32, %arg5: i1):
      %2 = comb.add %arg3, %arg4 : i32
      pipeline.stage.return regs %2 valid %arg5 : (i32)
    }
    pipeline.return %output valid %valid : i32
  }
  hw.output %1 : i32
}

Inline lowering

All operations are inlined directly into the parent scope of the pipeline.pipeline:

  hw.module @testMultiple(%arg0: i32, %arg1: i32, %go: i1, %clk: i1, %rst: i1) -> (out: i32) {
    %0 = comb.add %arg0, %arg1 : i32
    %p0_s0_reg0 = seq.compreg %0, %clk : i32
    %p0_s0_valid = seq.compreg %go, %clk : i1
    %1 = comb.add %p0_s0_reg0, %p0_s0_reg0 : i32
    %p1_s0_reg0 = seq.compreg %1, %clk : i32
    %p1_s0_valid = seq.compreg %go, %clk : i1
    hw.output %p1_s0_reg0 : i32
  }

Outline lowering

All stages and the pipeline itself are outlined into separate modules. The pipeline will contain instantiations of the stages of which it is comprised. There will be a single instantiation of the pipeline module at the pipeline.pipeline location.

  hw.module @testMultiple_p0(%in0: i32, %in1: i32, %in2: i1, %clk: i1, %rst: i1) -> (out0: i32) {
    %testMultiple_p0_s0.out0, %testMultiple_p0_s0.valid = hw.instance "testMultiple_p0_s0" @testMultiple_p0_s0(in0: %in0: i32, in1: %in1: i32, enable: %in2: i1, clk: %clk: i1, rst: %rst: i1) -> (out0: i32, valid: i1)
    hw.output %testMultiple_p0_s0.out0 : i32
  }
  hw.module @testMultiple_p0_s0(%in0: i32, %in1: i32, %enable: i1, %clk: i1, %rst: i1) -> (out0: i32, valid: i1) {
    %0 = comb.add %in0, %in1 : i32
    %s0_reg0 = seq.compreg %0, %clk : i32
    %s0_valid = seq.compreg %enable, %clk : i1
    hw.output %s0_reg0, %s0_valid : i32, i1
  }
  hw.module @testMultiple_p1(%in0: i32, %in1: i32, %in2: i1, %clk: i1, %rst: i1) -> (out0: i32) {
    %testMultiple_p1_s0.out0, %testMultiple_p1_s0.valid = hw.instance "testMultiple_p1_s0" @testMultiple_p1_s0(in0: %in0: i32, in1: %in1: i32, enable: %in2: i1, clk: %clk: i1, rst: %rst: i1) -> (out0: i32, valid: i1)
    hw.output %testMultiple_p1_s0.out0 : i32
  }
  hw.module @testMultiple_p1_s0(%in0: i32, %in1: i32, %enable: i1, %clk: i1, %rst: i1) -> (out0: i32, valid: i1) {
    %0 = comb.add %in0, %in1 : i32
    %s0_reg0 = seq.compreg %0, %clk : i32
    %s0_valid = seq.compreg %enable, %clk : i1
    hw.output %s0_reg0, %s0_valid : i32, i1
  }
  hw.module @testMultiple(%arg0: i32, %arg1: i32, %go: i1, %clk: i1, %rst: i1) -> (out: i32) {
    %testMultiple_p0.out0 = hw.instance "testMultiple_p0" @testMultiple_p0(in0: %arg0: i32, in1: %arg1: i32, in2: %go: i1, clk: %clk: i1, rst: %rst: i1) -> (out0: i32)
    %testMultiple_p1.out0 = hw.instance "testMultiple_p1" @testMultiple_p1(in0: %testMultiple_p0.out0: i32, in1: %testMultiple_p0.out0: i32, in2: %go: i1, clk: %clk: i1, rst: %rst: i1) -> (out0: i32)
    hw.output %testMultiple_p1.out0 : i32
  }

@mortbopet mortbopet requested a review from teqdruid May 19, 2023 19:38
@mortbopet mortbopet marked this pull request as ready for review May 22, 2023 07:15
@mortbopet mortbopet marked this pull request as draft May 22, 2023 09:07
@mortbopet mortbopet force-pushed the dev/mpetersen/pipeline_outline_hw branch from 74b0c35 to 5072355 Compare May 24, 2023 12:50
@mortbopet mortbopet changed the base branch from main to dev/mpetersen/stage_register May 24, 2023 12:50
@mortbopet mortbopet requested a review from mikeurbach May 24, 2023 12:51
@mortbopet mortbopet marked this pull request as ready for review May 24, 2023 12:51
@mortbopet mortbopet force-pushed the dev/mpetersen/pipeline_outline_hw branch from 5072355 to 3c688ab Compare May 24, 2023 12:57
@mortbopet mortbopet changed the title [PipelineToHW] Add "outlined" lowering [PipelineToHW] Rework hardware lowering May 24, 2023
@mikeurbach
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Just curious, what is the motivation for the outlined lowering? It seems this is what motivated the new pipeline.stage representation, but personally I would use the inline lowering.

@teqdruid
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Certain RTL compilers only do resource reporting at the module granularity. Users often want to have resource usage information at the stage granularity.

@mortbopet mortbopet force-pushed the dev/mpetersen/pipeline_outline_hw branch from 3c688ab to b4b701d Compare May 25, 2023 08:51
mortbopet added a commit that referenced this pull request May 26, 2023
This signal is intended to connect to all stages within the pipeline, and is used to stall the entirety of the pipeline. It is lowering defined how stages choose to use this signal, although in the common case, a `stall` signal would typically connect to the clock-enable input of the stage-separating registers.

Future PRs will implement hardware lowerings - blocked by #5234.
@mortbopet mortbopet force-pushed the dev/mpetersen/stage_register branch from 89e5c4c to be20f7e Compare May 30, 2023 07:53
@mortbopet mortbopet force-pushed the dev/mpetersen/pipeline_outline_hw branch from b4b701d to 0d88451 Compare May 30, 2023 07:59
This PR reworks hardware lowering to be based on the new `pipeline.stage` operation introduced in #5246.

Two lowering options are available, inline and outline lowering.

Given an input:
```mlir
hw.module @testMultiple(%arg0 : i32, %arg1 : i32, %go : i1, %clk : i1, %rst : i1) -> (out: i32) {
  %0 = pipeline.pipeline(%arg0, %arg1, %go) clock %clk reset %rst : (i32, i32, i1) -> i32 {
  ^bb0(%arg0_0: i32, %arg1_1: i32, %arg2: i1):
    %output, %valid = pipeline.stage ins %arg0_0, %arg1_1 enable %arg2 : (i32, i32) -> (i32) {
    ^bb0(%arg3: i32, %arg4: i32, %arg5: i1):
      %2 = comb.add %arg3, %arg4 : i32
      pipeline.stage.return regs %2 valid %arg5 : (i32)
    }
    pipeline.return %output valid %valid : i32
  }
  %1 = pipeline.pipeline(%0, %0, %go) clock %clk reset %rst : (i32, i32, i1) -> i32 {
  ^bb0(%arg0_0: i32, %arg1_1: i32, %arg2: i1):
    %output, %valid = pipeline.stage ins %arg0_0, %arg1_1 enable %arg2 : (i32, i32) -> (i32) {
    ^bb0(%arg3: i32, %arg4: i32, %arg5: i1):
      %2 = comb.add %arg3, %arg4 : i32
      pipeline.stage.return regs %2 valid %arg5 : (i32)
    }
    pipeline.return %output valid %valid : i32
  }
  hw.output %1 : i32
}
```

All operations are inlined directly into the parent scope of the `pipeline.pipeline`:

```mlir
  hw.module @testMultiple(%arg0: i32, %arg1: i32, %go: i1, %clk: i1, %rst: i1) -> (out: i32) {
    %0 = comb.add %arg0, %arg1 : i32
    %p0_s0_reg0 = seq.compreg %0, %clk : i32
    %p0_s0_valid = seq.compreg %go, %clk : i1
    %1 = comb.add %p0_s0_reg0, %p0_s0_reg0 : i32
    %p1_s0_reg0 = seq.compreg %1, %clk : i32
    %p1_s0_valid = seq.compreg %go, %clk : i1
    hw.output %p1_s0_reg0 : i32
  }
```

All stages and the pipeline itself are outlined into separate modules. The pipeline will contain instantiations of the stages of which it is comprised. There will be a single instantiation of the pipeline module at the `pipeline.pipeline` location.

```mlir
  hw.module @testMultiple_p0(%in0: i32, %in1: i32, %in2: i1, %clk: i1, %rst: i1) -> (out0: i32) {
    %testMultiple_p0_s0.out0, %testMultiple_p0_s0.valid = hw.instance "testMultiple_p0_s0" @testMultiple_p0_s0(in0: %in0: i32, in1: %in1: i32, enable: %in2: i1, clk: %clk: i1, rst: %rst: i1) -> (out0: i32, valid: i1)
    hw.output %testMultiple_p0_s0.out0 : i32
  }
  hw.module @testMultiple_p0_s0(%in0: i32, %in1: i32, %enable: i1, %clk: i1, %rst: i1) -> (out0: i32, valid: i1) {
    %0 = comb.add %in0, %in1 : i32
    %s0_reg0 = seq.compreg %0, %clk : i32
    %s0_valid = seq.compreg %enable, %clk : i1
    hw.output %s0_reg0, %s0_valid : i32, i1
  }
  hw.module @testMultiple_p1(%in0: i32, %in1: i32, %in2: i1, %clk: i1, %rst: i1) -> (out0: i32) {
    %testMultiple_p1_s0.out0, %testMultiple_p1_s0.valid = hw.instance "testMultiple_p1_s0" @testMultiple_p1_s0(in0: %in0: i32, in1: %in1: i32, enable: %in2: i1, clk: %clk: i1, rst: %rst: i1) -> (out0: i32, valid: i1)
    hw.output %testMultiple_p1_s0.out0 : i32
  }
  hw.module @testMultiple_p1_s0(%in0: i32, %in1: i32, %enable: i1, %clk: i1, %rst: i1) -> (out0: i32, valid: i1) {
    %0 = comb.add %in0, %in1 : i32
    %s0_reg0 = seq.compreg %0, %clk : i32
    %s0_valid = seq.compreg %enable, %clk : i1
    hw.output %s0_reg0, %s0_valid : i32, i1
  }
  hw.module @testMultiple(%arg0: i32, %arg1: i32, %go: i1, %clk: i1, %rst: i1) -> (out: i32) {
    %testMultiple_p0.out0 = hw.instance "testMultiple_p0" @testMultiple_p0(in0: %arg0: i32, in1: %arg1: i32, in2: %go: i1, clk: %clk: i1, rst: %rst: i1) -> (out0: i32)
    %testMultiple_p1.out0 = hw.instance "testMultiple_p1" @testMultiple_p1(in0: %testMultiple_p0.out0: i32, in1: %testMultiple_p0.out0: i32, in2: %go: i1, clk: %clk: i1, rst: %rst: i1) -> (out0: i32)
    hw.output %testMultiple_p1.out0 : i32
  }
```
@mortbopet mortbopet force-pushed the dev/mpetersen/pipeline_outline_hw branch from 0d88451 to d09e2db Compare June 1, 2023 08:34
@mortbopet mortbopet changed the base branch from dev/mpetersen/stage_register to main June 1, 2023 08:37
@mortbopet
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I will preemptively merge this and then schedule a post-merge review, seeing as @teqdruid most likely is going to need this today.

@mortbopet mortbopet merged commit 74ddda5 into main Jun 1, 2023
mortbopet added a commit that referenced this pull request Jun 12, 2023
This signal is intended to connect to all stages within the pipeline, and is used to stall the entirety of the pipeline. It is lowering defined how stages choose to use this signal, although in the common case, a `stall` signal would typically connect to the clock-enable input of the stage-separating registers.

Future PRs will implement hardware lowerings - blocked by #5234.
@darthscsi darthscsi deleted the dev/mpetersen/pipeline_outline_hw branch June 4, 2024 14:48
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3 participants