[Pipeline] Add "ext" inputs to pipelines

[mortbopet]

ext inputs are inputs which are accessible in any pipeline stage, and which will never be registered during register materialization. If you imagine a pipeline as signals going from left to right with registers in between, ext inputs are inputs that hook in from the top or bottom, into any pipeline stage.

In hardware (outlined) lowering, the external inputs are only provided to stages which actually reference them:

hw.module @testSingleWithExt(%arg0: i32, %ext1: i32, %clk: i1, %rst: i1) -> (out0: i32, out1: i32) {
  %0:2 = pipeline.scheduled(%arg0, %arg0) ext (%ext1 : i32) clock %clk reset %rst : (i32, i32) -> (i32, i32) {
  ^bb0(%a0: i32, %a1 : i32, %ext0: i32):
    %true = hw.constant true
    %1 = comb.sub %a0, %a0 : i32
    pipeline.stage ^bb1 regs(%1 : i32) enable %true

  ^bb1(%6: i32):
    // Use the external value inside a stage
    %8 = comb.add %6, %ext0 : i32
    pipeline.stage ^bb2 regs(%8 : i32) enable %true
  
  ^bb2(%9 : i32):
  // Use the external value in the exit stage.
    pipeline.return %9, %ext0  : i32, i32
  }
  hw.output %0#0, %0#1 : i32, i32
}

// lowers to
  hw.module @testSingleWithExt_p0(%in0: i32, %in1: i32, %extIn0: i32, %clk: i1, %rst: i1) -> (out0: i32, out1: i32) {
    %testSingleWithExt_p0_s0.out0 = hw.instance "testSingleWithExt_p0_s0" @testSingleWithExt_p0_s0(in0: %in0: i32, in1: %in1: i32, clk: %clk: i1, rst: %rst: i1) -> (out0: i32)
    %testSingleWithExt_p0_s1.out0 = hw.instance "testSingleWithExt_p0_s1" @testSingleWithExt_p0_s1(in0: %testSingleWithExt_p0_s0.out0: i32, extIn0: %extIn0: i32, clk: %clk: i1, rst: %rst: i1) -> (out0: i32)
    hw.output %testSingleWithExt_p0_s1.out0, %extIn0 : i32, i32
  }
  hw.module @testSingleWithExt_p0_s0(%in0: i32, %in1: i32, %clk: i1, %rst: i1) -> (out0: i32) {
    %true = hw.constant true
    %0 = comb.sub %in0, %in0 : i32
    %s0_reg0 = seq.compreg %0, %clk : i32
    hw.output %s0_reg0 : i32
  }
  hw.module @testSingleWithExt_p0_s1(%in0: i32, %extIn0: i32, %clk: i1, %rst: i1) -> (out0: i32) {
    %true = hw.constant true
    %0 = comb.add %in0, %extIn0 : i32
    %s1_reg0 = seq.compreg %0, %clk : i32
    hw.output %s1_reg0 : i32
  }
  hw.module @testSingleWithExt(%arg0: i32, %ext1: i32, %clk: i1, %rst: i1) -> (out0: i32, out1: i32) {
    %testSingleWithExt_p0.out0, %testSingleWithExt_p0.out1 = hw.instance "testSingleWithExt_p0" @testSingleWithExt_p0(in0: %arg0: i32, in1: %arg0: i32, extIn0: %ext1: i32, clk: %clk: i1, rst: %rst: i1) -> (out0: i32, out1: i32)
    hw.output %testSingleWithExt_p0.out0, %testSingleWithExt_p0.out1 : i32, i32
  }

Note: The pipeline op signature is getting unruly, given that all inputs are bundled into the single ^bb0 definition. In a future commit, i plan to specialize the printer/parser for the pipeline op to mimick something like the scf ops, such that we have a bit more sane format.

  %out:2 = pipeline.scheduled(%arg0) ext(%arg1 : i32) clock %clk reset %rst : (i32, i32) -> (i32, i32) {
    ^bb0(%a0 : i32, %ext0: i32):

// vs

%out:2 = pipeline.scheduled(%a0 : i32 = %arg0) ext(%ext0 = %arg1 : i32) clock %clk reset %rst -> (i32, i32) {

[teqdruid]

thanks!

[teqdruid]

I am uncomfortable with making the assumption that the inputs are the first group of block args, but I don't think there's any alternative. Matt was commenting on something similar (having to rely on port numbers rather than named symbols). You might think on a solution for both and if the problems relate.

Just something I want to put in your brain.

[teqdruid]

For this, is there anything that ODS generates which could be used to get the offset? (Which would be zero with the current ODS def.)

[mortbopet]

Changed to

  return stage->getArguments().slice(getInputs().getBeginOperandIndex(), getInputs().size());

[teqdruid]

Magic constants. Eww. Can you define some (perhaps public) offset constants for these? Or an attribute? We should really come up with an efficient way to access port indexes by name.