[FIRRTL] Add mux cell intrinsics #5428
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This commit adds intrinscis (int.synopsys.mux4, mux2) for directely representing 4-to-1 and 2-to1 MUX cells in the synopys backend. With these operations, we can construct N-to-1 mux opitmized for synopsys target at the Chisel level This commit includes ODS definition, LowerTypes, InferWith, and folder change (only for mux2).
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Changed to common operations based on the offline discussion |
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This commit adds intrinsics (int.muxcell4, muxcell2) for directely representing 4-wide and 2-wide MUX cells in the backend. With these operations, we can construct N-to-1 mux at the Chisel level.
This commit includes ODS definition, LowerIntrinsic, LowerTypes, InferWith, and folder change (only for mux2).
LowerToHW change will be done after #5427 which would require more iterations.