[SeqToSV] Add clock_gate lowering

[mortbopet]

... for those times when you don't want to externalize a clock gate. My immediate use for this is to not have to worry about placing clock gate modules into output/search folders when running integration tests for ops that use clock gates. Obviously, the clock gate externalization pass can be run prior to SV lowering to skip this. Secondly, i prefer that all ops have some way of reaching emission without having to worry about external collateral.

The implementation exports as the following sv:

module cg1(
  input  clk,
         enable,
  output gclk
);

  reg cg_en_latch;
  always @(edge clk or edge enable) begin
    if (~clk)
      cg_en_latch <= enable;
  end
  assign gclk = clk & cg_en_latch;
endmodule

module cg2(
  input  clk,
         enable,
         test_enable,
  output gclk
);

  wire _GEN = enable | test_enable;
  reg  cg_en_latch;
  always @(edge clk or edge _GEN) begin
    if (~clk)
      cg_en_latch <= _GEN;
  end
  assign gclk = clk & cg_en_latch;
endmodule

[fabianschuiki]

LGTM! Thanks for adding this. 💯