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[SeqToSV] Add clock_gate lowering #5457

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Jun 26, 2023
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[SeqToSV] Add clock_gate lowering #5457

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46 changes: 45 additions & 1 deletion lib/Dialect/Seq/Transforms/LowerSeqToSV.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -135,6 +135,49 @@ class CompRegLower : public OpConversionPattern<OpTy> {
private:
bool lowerToAlwaysFF;
};

// Lower seq.clock_gate to a fairly standard clock gate implementation.
//
class ClockGateLowering : public OpConversionPattern<ClockGateOp> {
public:
using OpConversionPattern<ClockGateOp>::OpConversionPattern;
using OpAdaptor = typename OpConversionPattern<ClockGateOp>::OpAdaptor;
LogicalResult
matchAndRewrite(ClockGateOp clockGate, OpAdaptor adaptor,
ConversionPatternRewriter &rewriter) const final {
auto loc = clockGate.getLoc();
Value clk = adaptor.getInput();

// enable in
Value enable = adaptor.getEnable();
if (auto te = adaptor.getTestEnable())
enable = rewriter.create<comb::OrOp>(loc, enable, te);

// Enable latch.
Value enableLatch = rewriter.create<sv::RegOp>(
loc, rewriter.getI1Type(), rewriter.getStringAttr("cg_en_latch"));

// Latch the enable signal.
rewriter.create<sv::AlwaysOp>(
loc,
llvm::SmallVector<sv::EventControl>{sv::EventControl::AtEdge,
sv::EventControl::AtEdge},
llvm::SmallVector<Value>{clk, enable}, [&]() {
rewriter.create<sv::IfOp>(
loc, comb::createOrFoldNot(loc, clk, rewriter), [&]() {
rewriter.create<sv::PAssignOp>(loc, enableLatch, enable);
});
});

// Create the gated clock signal.
Value gclk = rewriter.create<comb::AndOp>(
loc, clk, rewriter.create<sv::ReadInOutOp>(loc, enableLatch));
clockGate.replaceAllUsesWith(gclk);
rewriter.eraseOp(clockGate);
return success();
}
};

} // namespace

namespace {
Expand Down Expand Up @@ -772,10 +815,11 @@ void SeqToSVPass::runOnOperation() {
MLIRContext &ctxt = getContext();
ConversionTarget target(ctxt);
target.addIllegalDialect<SeqDialect>();
target.addLegalDialect<sv::SVDialect>();
target.addLegalDialect<sv::SVDialect, comb::CombDialect, hw::HWDialect>();
RewritePatternSet patterns(&ctxt);
patterns.add<CompRegLower<CompRegOp>>(&ctxt, lowerToAlwaysFF);
patterns.add<CompRegLower<CompRegClockEnabledOp>>(&ctxt, lowerToAlwaysFF);
patterns.add<ClockGateLowering>(&ctxt);

if (failed(applyPartialConversion(top, target, std::move(patterns))))
signalPassFailure();
Expand Down
40 changes: 40 additions & 0 deletions test/Dialect/Seq/clock-gate.mlir
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Original file line number Diff line number Diff line change
@@ -0,0 +1,40 @@
// RUN: circt-opt --lower-seq-to-sv %s | FileCheck %s

// CHECK-LABEL: hw.module @cg1(
// CHECK-SAME: %[[VAL_0:.*]]: i1, %[[VAL_1:.*]]: i1) -> (gclk: i1) {
// CHECK: %[[VAL_2:.*]] = sv.reg : !hw.inout<i1>
// CHECK: sv.always edge %[[VAL_0]], edge %[[VAL_1]] {
// CHECK: %[[VAL_3:.*]] = hw.constant true
// CHECK: %[[VAL_4:.*]] = comb.xor %[[VAL_0]], %[[VAL_3]] : i1
// CHECK: sv.if %[[VAL_4]] {
// CHECK: sv.passign %[[VAL_2]], %[[VAL_1]] : i1
// CHECK: }
// CHECK: }
// CHECK: %[[VAL_5:.*]] = sv.read_inout %[[VAL_2]] : !hw.inout<i1>
// CHECK: %[[VAL_6:.*]] = comb.and %[[VAL_0]], %[[VAL_5]] : i1
// CHECK: hw.output %[[VAL_6]] : i1
// CHECK: }
hw.module @cg1(%clk : i1, %enable : i1) -> (gclk : i1) {
%0 = seq.clock_gate %clk, %enable
hw.output %0 : i1
}

// CHECK-LABEL: hw.module @cg2(
// CHECK-SAME: %[[VAL_0:.*]]: i1, %[[VAL_1:.*]]: i1, %[[VAL_2:.*]]: i1) -> (gclk: i1) {
// CHECK: %[[VAL_3:.*]] = comb.or %[[VAL_1]], %[[VAL_2]] : i1
// CHECK: %[[VAL_4:.*]] = sv.reg : !hw.inout<i1>
// CHECK: sv.always edge %[[VAL_0]], edge %[[VAL_3]] {
// CHECK: %[[VAL_5:.*]] = hw.constant true
// CHECK: %[[VAL_6:.*]] = comb.xor %[[VAL_0]], %[[VAL_5]] : i1
// CHECK: sv.if %[[VAL_6]] {
// CHECK: sv.passign %[[VAL_4]], %[[VAL_3]] : i1
// CHECK: }
// CHECK: }
// CHECK: %[[VAL_7:.*]] = sv.read_inout %[[VAL_4]] : !hw.inout<i1>
// CHECK: %[[VAL_8:.*]] = comb.and %[[VAL_0]], %[[VAL_7]] : i1
// CHECK: hw.output %[[VAL_8]] : i1
// CHECK: }
hw.module @cg2(%clk : i1, %enable : i1, %test_enable : i1) -> (gclk : i1) {
%0 = seq.clock_gate %clk, %enable, %test_enable
hw.output %0 : i1
}