[FIRRTL] Relax ODS defined FIRRTL base subtypes to allow type aliases #5652
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uenoku
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prithayan
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Jul 27, 2023
| @@ -1042,7 +1042,7 @@ void Emitter::emitExpression(SpecialConstantOp op) { | |||
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| // NOLINTNEXTLINE(misc-no-recursion) | |||
| void Emitter::emitExpression(SubfieldOp op) { | |||
| auto type = op.getInput().getType(); | |||
| BundleType type = op.getInput().getType(); | |||
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The implicit casts are helpful !!
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uenoku
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| @@ -46,17 +46,19 @@ circuit test_mod : %[[{"class": "circt.testNT", "data": "a"}]] | |||
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| ; VERILOG-IR: sv.verbatim{{.*}}Standard header to adapt well known macros to our needs | |||
| ; VERILOG-IR: sv.macro.def @INIT_RANDOM_PROLOG_ | |||
| type V3 = UInt<1>[3] | |||
| type V2 = UInt<1>[2] | |||
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| module test_mod : | |||
| input clock : Clock | |||
| input a: UInt<1> | |||
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It seems type alias for integers is not well supported in HW/Comb. There are still a lot of places where normal llvm casts are used. So i added type alias only for vectors.
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This PR introduces
BaseTypeAliasOrhelper struct to create a type which accepts both type aliases and a specified type.Unfortunately this PR makes it hard to use
TypedValue<Foo>which is returned by standard ODS generated getters since now the type will becomeTypedValue<BaseTypeAliasOr<Foo>>.