[FIRRTL] Preserve port orders when lowering to HW. #6224
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seldridge
approved these changes
Sep 29, 2023
dtzSiFive
approved these changes
Oct 2, 2023
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LGTM! Awesome that in the end this change is all that's needed to flip over!
- Looks like this is more of an HW change than FIRRTL, changes builder helper to no longer group inputs then outputs?
- This seems worth having an explicit test for (not just implicit testing via tests for other things). A small direct one would be great.
| ; NOREFS-NEXT: .R7_data (memTap_1), | ||
| ; NOREFS-NEXT: .R8_data (memTap_0) | ||
| ; NOREFS-NEXT: ) | ||
| ; NOREFS: .R2_data (memTap_6), |
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Please add whitespace (5 spaces) to restore the alignment.
Interesting, these are interleaved now! 🤔 .
| @@ -246,11 +246,13 @@ circuit TestHarness : %[[ | |||
| ; CHECK: module Top( | |||
| ; CHECK-NOT: endmodule | |||
| ; CHECK: Companion Companion ( | |||
| ; CHECK: .io (io), | |||
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| ; CHECK: .io (io), | |
| ; CHECK-NEXT: .io (io), |
| ; CHECK-NEXT: .[[bore:[a-zA-Z0-9_]+]] (Top.test.signal_probe) | ||
| ; CHECK: endmodule | ||
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| ; CHECK: module Companion( | ||
| ; CHECK-NOT: endmodule | ||
| ; CHECK: output io, |
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| ; CHECK: output io, | |
| ; CHECK-NEXT: output io, |
| return updatedName.cast<StringAttr>().getValue(); | ||
| // Get the original name of input port if no renaming. | ||
| return cast<HWModuleLike>(module).getPortName(portArgNum); | ||
| return getPortVerilogName(module, htmo.getPortList().atInput(portArgNum)); |
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Can this just access both of them via PortList interface? getPortVerilogName(module, cast<PortList>(module).getPortList().atInput(portArgNum)) or so?
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This function should be going away soon.
mikeurbach
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that referenced
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Oct 2, 2023
Move lower to hw to preserve port order instead of doing inputs then outputs.
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