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[FIRRTL] Limited invalid propagation. #7074

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merged 5 commits into from
May 22, 2024
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darthscsi
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Now that invalid is better defined, we can start propagating it when we can preserver semantics. This means not breaking the one-op-is-one-consistent-value (e.g. not duplicating). The only bit mutating op which is touched by this change is not, which is a pure all-bits inversion, which should be safe (tm).

Now that invalid is better defined, we can start propagating it when we can preserver semantics.  This means not breaking the one-op-is-one-consistent-value (e.g. not duplicating).  The only bit mutating op which is touched by this change is not, which is a pure all-bits inversion, which should be safe (tm).
// can you propagate through binary ops.
if (op->hasOneUse() &&
isa<BitsPrimOp, HeadPrimOp, ShrPrimOp, TailPrimOp, SubfieldOp, SubindexOp,
AsSIntPrimOp, AsUIntPrimOp, NotPrimOp>(*op->user_begin())) {
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There are a few more unwary ops that can be included: cvt, pad, asClock, and the reduction ops.

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Pad adds bits, so it isn't safe, cvt interprets the bits and can add bits, so likewise. asClock is probably safe.

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But reductions are a good call.

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oddly, a reduction of a zero-width value is NOT invalid, even though all other widths are.

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This is legal per the spec. Can you check the impact on a real design? 🧐

I'm also starting to question if CSE involving invalid value ops is going to make much of this rare to canonicalize.

Re: rarity: do we propagate invalid through single connects with your new wire to node conversion? It's pretty difficult to create an invalid in Chisel as it has to be of a component. Practically, this usually shows up on only ports or wires and both of these are funneling invalid through a connect.

test/Dialect/FIRRTL/canonicalization.mlir Show resolved Hide resolved
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Doesn't seem to have any effect on at least one large design.

@darthscsi darthscsi merged commit 946caf9 into main May 22, 2024
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@darthscsi darthscsi deleted the dev/darthscsi/propInvalid branch May 22, 2024 16:37
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2 participants