[GlobalISel] getICmpResultType and getFCmpResultType

[tschuett]

TargetLowering has

/// Return the ValueType of the result of SETCC operations.
  virtual EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
                                 EVT VT) const;

Should we add similar hooks to target lowering?
Add virtual = 0 functions to LegalizerInfo and every target has to implement them?

I looked through the internals of LegalizerInfo, but I failed to sneak out the result types.

[SelectionDAG] Expand [US]CMP using arithmetic on boolean values instead of selects
#98774

relies on the result type of setccs.

Alternvatives?

[tschuett]

EVT AArch64TargetLowering::getSetCCResultType(const DataLayout &,
                                              LLVMContext &C, EVT VT) const {
  if (!VT.isVector())
    return MVT::i32;
  if (VT.isScalableVector())
    return EVT::getVectorVT(C, MVT::i1, VT.getVectorElementCount());
  return VT.changeVectorElementTypeToInteger();
}

[arsenm]

We could add an LLT variant of this, but it's less critical than in SelectionDAG. Since the legalizer does not have phases like the DAG, you can always just use s1 and let the boolean operations legalize to whatever type the legalize rules say to use.

The hook could save a legalization step, and is more useful post-legalization. I don't think we should split these into separate icmp and fcmp variants. In practice this means the type to use in all boolean contexts. I do not think it's useful to try to support different result types for the different compares

[tschuett]

#98774 exploits knowledge of the icmp result type. The GlobalISel variant assumes s1 as the result type #119265. The code looks different.

[tschuett]

My markdown prototype:

// RISC-V

LLT getICmpResultType(LLT LHS) const override {
  unsigned XLen = STI.getXLen();
  if (LHS.isScalar())
    return LLT::scalar(XLen);

  return LLT::vector(LLT::scalar(1), LHS.getElementCount());
}

LLT getFCmpResultType(LLT LHS) const override {
  unsigned XLen = STI.getXLen();

  return LLT::scalar(XLen);
}


// AArch64

LLT getICmpResultType(LLT LHS) const override {
  if (LHS.isScalableVector())
    return LLT::vector(LLT::scalar(1), LHS.getElementCount());
  if (LHS.isFixedVector())
    return LHS;

  return LLT::scalar(32);
}

LLT getFCmpResultType(LLT LHS) const override {
  if (LHS.isScalableVector())
    return LLT::vector(LLT::scalar(1), LHS.getElementCount());
  if (LHS.isFixedVector())
    return LHS;

  return LLT::scalar(32);
}

I found no vector support for fcmps for RISCV-V.

[arsenm]

For AMDGPU this will depend on the register banks of the values. We need to use s1 or s32 depending on the use context

[tschuett]

Could you prototype an alternative signature/function that serves your needs?