[X86] lowerFPToIntToFP - handle UI2FP on AVX512VL targets and i64 types on AVX512DQ targets

[RKSimon]

https://zig.godbolt.org/z/v3rqr86P1

We attempt to vectorize scalar fp->int->fp round trips to avoid transfer from the FPU to the GPRs and back again:

define double @scvtf64_i32(double %a0) {
    %ii = fptosi double %a0 to i32
    %ff = sitofp i32 %ii to double
    ret double %ff
}
define float @scvtf32_i32(float %a0) {
    %ii = fptosi float %a0 to i32
    %ff = sitofp i32 %ii to float
    ret float %ff
}

scvtf64_i32: # @scvtf64_i32
  vcvttpd2dq %xmm0, %xmm0
  vcvtdq2pd %xmm0, %xmm0
  retq
scvtf32_i32: # @scvtf32_i32
  vcvttps2dq %xmm0, %xmm0
  vcvtdq2ps %xmm0, %xmm0
  retq

This is currently only performed for f64/32 <-> i32 legal SSE2+ FP_TO_SINT/SINT_TO_FP conversions.

AVX512VL could handle this for FP_TO_UINT/UINT_TO_FP conversions as well (AVX512F if we widen to 512-bits instead of 128-bit).

AV512DQ+AVX512VL could handle this for f64/32 <-> i64 SINT and UINT conversions as well.

This will require adjusting lowerFPToIntToFP to recognize FP_TO_UINT/UINT_TO_FP patterns on AVX512VL targets and i64 scalars on AV512DQ+AVX512VL targets, along with any additional test coverage that we don't already have.

[llvmbot]

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[llvmbot]

@llvm/issue-subscribers-good-first-issue

Author: Simon Pilgrim (RKSimon)

https://zig.godbolt.org/z/v3rqr86P1

We attempt to vectorize scalar fp->int->fp round trips to avoid transfer from the FPU to the GPRs and back again:

define double @<!-- -->scvtf64_i32(double %a0) {
    %ii = fptosi double %a0 to i32
    %ff = sitofp i32 %ii to double
    ret double %ff
}
define float @<!-- -->scvtf32_i32(float %a0) {
    %ii = fptosi float %a0 to i32
    %ff = sitofp i32 %ii to float
    ret float %ff
}

scvtf64_i32: # @<!-- -->scvtf64_i32
  vcvttpd2dq %xmm0, %xmm0
  vcvtdq2pd %xmm0, %xmm0
  retq
scvtf32_i32: # @<!-- -->scvtf32_i32
  vcvttps2dq %xmm0, %xmm0
  vcvtdq2ps %xmm0, %xmm0
  retq

This is currently only performed for f64/32 <-> i32 legal SSE2+ FP_TO_SINT/SINT_TO_FP conversions.

AVX512VL could handle this for FP_TO_UINT/UINT_TO_FP conversions as well (AVX512F if we widen to 512-bits instead of 128-bit).

AV512DQ+AVX512VL could handle this for f64/32 <-> i64 SINT and UINT conversions as well.

This will require adjusting lowerFPToIntToFP to recognize FP_TO_UINT/UINT_TO_FP patterns on AVX512VL targets and i64 scalars on AV512DQ+AVX512VL targets, along with any additional test coverage that we don't already have.

[llvmbot]

@llvm/issue-subscribers-backend-x86

Author: Simon Pilgrim (RKSimon)

https://zig.godbolt.org/z/v3rqr86P1

We attempt to vectorize scalar fp->int->fp round trips to avoid transfer from the FPU to the GPRs and back again:

define double @<!-- -->scvtf64_i32(double %a0) {
    %ii = fptosi double %a0 to i32
    %ff = sitofp i32 %ii to double
    ret double %ff
}
define float @<!-- -->scvtf32_i32(float %a0) {
    %ii = fptosi float %a0 to i32
    %ff = sitofp i32 %ii to float
    ret float %ff
}

scvtf64_i32: # @<!-- -->scvtf64_i32
  vcvttpd2dq %xmm0, %xmm0
  vcvtdq2pd %xmm0, %xmm0
  retq
scvtf32_i32: # @<!-- -->scvtf32_i32
  vcvttps2dq %xmm0, %xmm0
  vcvtdq2ps %xmm0, %xmm0
  retq

This is currently only performed for f64/32 <-> i32 legal SSE2+ FP_TO_SINT/SINT_TO_FP conversions.

AVX512VL could handle this for FP_TO_UINT/UINT_TO_FP conversions as well (AVX512F if we widen to 512-bits instead of 128-bit).

AV512DQ+AVX512VL could handle this for f64/32 <-> i64 SINT and UINT conversions as well.

This will require adjusting lowerFPToIntToFP to recognize FP_TO_UINT/UINT_TO_FP patterns on AVX512VL targets and i64 scalars on AV512DQ+AVX512VL targets, along with any additional test coverage that we don't already have.

[KavinTheG]

Hi @RKSimon, may I be assigned this issue?

[KavinTheG]

Hey @RKSimon, I opened up a draft PR. Not sure if I'm on the right track.

[KavinTheG]

Sorry for the delay, I'm a bit confused on what test cases I can add. I took a look at what I believe to be the appropriate files, scalar-int-to-fp.ll, scalar-fp-to-int32.ll, and scalar-fp-to-int64.ll and it seems like these files cover the necessary cases?

rg "define" ../llvm/test/CodeGen/X86/scalar-fp-to-i32.ll

30:define i32 @f_to_u32(float %a) nounwind {
108:define i32 @f_to_s32(float %a) nounwind {
147:define i32 @d_to_u32(double %a) nounwind {
283:define i32 @d_to_s32(double %a) nounwind {
342:define i32 @x_to_u32(x86_fp80 %a) nounwind {
552:define i32 @x_to_s32(x86_fp80 %a) nounwind {
762:define i32 @t_to_u32(fp128 %a) nounwind {
876:define i32 @t_to_s32(fp128 %a) nounwind {

rg "define" ../llvm/test/CodeGen/X86/scalar-fp-to-i64.ll

41:define i64 @f_to_u64(float %a) nounwind {
311:define i64 @f_to_s64(float %a) nounwind {
474:define i64 @d_to_u64(double %a) nounwind {
744:define i64 @d_to_s64(double %a) nounwind {
907:define i64 @x_to_u64(x86_fp80 %a) nounwind {
1233:define i64 @x_to_s64(x86_fp80 %a) nounwind {
1417:define i64 @t_to_u64(fp128 %a) nounwind {
1531:define i64 @t_to_s64(fp128 %a) nounwind {

rg "define" ../llvm/test/CodeGen/X86/scalar-int-to-fp.ll

17:define float @u32_to_f(i32 %a) nounwind {
83:define float @s32_to_f(i32 %a) nounwind {
124:define double @u32_to_d(i32 %a) nounwind {
195:define double @s32_to_d(i32 %a) nounwind {
253:define x86_fp80 @u32_to_x(i32 %a) nounwind {
278:define x86_fp80 @s32_to_x(i32 %a) nounwind {
297:define float @u64_to_f(i64 %a) nounwind {
426:define float @s64_to_f(i64 %a) nounwind {
485:define float @s64_to_f_2(i64 %a) nounwind {
611:define double @u64_to_d(i64 %a) nounwind {
733:define double @u64_to_d_optsize(i64 %a) nounwind optsize {
854:define double @s64_to_d(i64 %a) nounwind {
934:define double @s64_to_d_2(i64 %a) nounwind {
1066:define x86_fp80 @u64_to_x(i64 %a) nounwind {
1097:define x86_fp80 @s64_to_x(i64 %a) nounwind {

@RKSimon

[RKSimon]

@KavinTheG I'm adding additional test coverage at #162838 - the scalar-fp-to-int*.ll tests don't test the round trip patterns that we're interested in