[AArch64] Use zero register directly for inline assembly

[nathanchance]

Forwarded on from a downstream report: ClangBuiltLinux/linux#2127

GCC directly generates xzr or wzr for the rZ constraint when the %x or %w modifier are used, whereas clang always stores to an intermediate register.

void write_zero_x(volatile unsigned long *addr)
{
    asm volatile("str %x1, %0\n" : : "Qo" (*addr), "rZ" (0));
}

void write_zero_w(volatile unsigned long *addr)
{
    asm volatile("str %w1, %0\n" : : "Qo" (*addr), "rZ" (0));
}

GCC 15.2.0:

$ aarch64-linux-gcc -O2 -c test.c

$ llvm-objdump -dr test.o

test.o: file format elf64-littleaarch64

Disassembly of section .text:

0000000000000000 <write_zero_x>:
       0: f900001f      str     xzr, [x0]
       4: d65f03c0      ret

0000000000000008 <write_zero_w>:
       8: b900001f      str     wzr, [x0]
       c: d65f03c0      ret

clang @ cd33c6b:

$ clang --target=aarch64-linux -O2 -c test.c

$ llvm-objdump -dr test.o

test.o: file format elf64-littleaarch64

Disassembly of section .text:

0000000000000000 <write_zero_x>:
       0: 2a1f03e8      mov     w8, wzr
       4: f9000008      str     x8, [x0]
       8: d65f03c0      ret

000000000000000c <write_zero_w>:
       c: 2a1f03e8      mov     w8, wzr
      10: b9000008      str     w8, [x0]
      14: d65f03c0      ret

[llvmbot]

@llvm/issue-subscribers-backend-aarch64

Author: Nathan Chancellor (nathanchance)

Forwarded on from a downstream report: https://github.com/ClangBuiltLinux/linux/issues/2127

GCC directly generates xzr or wzr for the rZ constraint when the %x or %w modifier are used, whereas clang always stores to an intermediate register.

void write_zero_x(volatile unsigned long *addr)
{
    asm volatile("str %x1, %0\n" : : "Qo" (*addr), "rZ" (0));
}

void write_zero_w(volatile unsigned long *addr)
{
    asm volatile("str %w1, %0\n" : : "Qo" (*addr), "rZ" (0));
}

GCC 15.2.0:

$ aarch64-linux-gcc -O2 -c test.c

$ llvm-objdump -dr test.o

test.o: file format elf64-littleaarch64

Disassembly of section .text:

0000000000000000 <write_zero_x>:
       0: f900001f      str     xzr, [x0]
       4: d65f03c0      ret

0000000000000008 <write_zero_w>:
       8: b900001f      str     wzr, [x0]
       c: d65f03c0      ret

clang @ cd33c6b:

$ clang --target=aarch64-linux -O2 -c test.c

$ llvm-objdump -dr test.o

test.o: file format elf64-littleaarch64

Disassembly of section .text:

0000000000000000 <write_zero_x>:
       0: 2a1f03e8      mov     w8, wzr
       4: f9000008      str     x8, [x0]
       8: d65f03c0      ret

000000000000000c <write_zero_w>:
       c: 2a1f03e8      mov     w8, wzr
      10: b9000008      str     w8, [x0]
      14: d65f03c0      ret

[efriedma-quic]

In general, LLVM doesn't really support multiple different constraint letters for an inline asm operand, and it's difficult to implement well (see #20571). But maybe we can special-case "rZ" specifically.

[nickdesaulniers]

Does clang even support "Z" constraints? (Or "Y")

https://gcc.gnu.org/onlinedocs/gcc/Machine-Constraints.html

Z Integer constant zero

https://godbolt.org/z/3o6jaT51G

Seems like support for Z is broken, unless I'm misunderstanding its use.

[nathanchance]

Does clang even support "Z" constraints? (Or "Y")

Hmmm... I see one reference to Z in AArch64TargetLowering::getConstraintType() but nowhere else it seems. However, I do see references to a lowercase z constraint in AArch64TargetLowering::LowerAsmOperandForConstraint() that references xzr or wxr, which seems like it is what we may be looking for?

https://godbolt.org/z/7111qY9rz

It looks like z has been present since the initial arm64 port commit but I cannot find any references to z in GCC's history.

[efriedma-quic]

Yes, I think somehow gcc's "Z" is spelled "z" in LLVM.

Not surprised nobody noticed: it's a pretty useless constraint on its own, and LLVM currently doesn't allow using it with anything else.